2020-07-21 |
Luke Kenneth Casso... | whitespace |
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2020-07-21 |
Luke Kenneth Casso... | make cxxsim optional and print warning |
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2020-07-19 |
Luke Kenneth Casso... | use same write_vcd for cxxsim as pysim |
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2020-07-19 |
Luke Kenneth Casso... | fix bug in alu_fsm.py found by cxxsim: missing one... |
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2020-07-15 |
Luke Kenneth Casso... | use Record Assert and also check muxid |
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2020-07-14 |
Luke Kenneth Casso... | reduce code size by using CompOpSubsetBase for ALU... |
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2020-07-14 |
Luke Kenneth Casso... | attempting running cxxsim on ALU pipeline test |
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2020-07-12 |
Luke Kenneth Casso... | rename InternalOp to MicrOp |
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2020-07-11 |
Luke Kenneth Casso... | sorting out bigendian/littleendian including in qemu |
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2020-07-09 |
Luke Kenneth Casso... | also set so only if OE requires it |
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2020-07-09 |
Luke Kenneth Casso... | whoops test gets copied 4 times on the If. |
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2020-07-09 |
Luke Kenneth Casso... | ALU output stage, change logic slightly |
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2020-07-09 |
Luke Kenneth Casso... | clarifying comments on setting xer_ov/so |
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2020-07-08 |
Jacob Lifshay | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-07-06 |
Luke Kenneth Casso... | remove alu unneeded op record data |
tree | commitdiff |
2020-07-06 |
Luke Kenneth Casso... | remove alu unneeded op record data |
tree | commitdiff |
2020-07-06 |
Luke Kenneth Casso... | remove alu unneeded op record data |
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2020-07-05 |
Luke Kenneth Casso... | big reorg on PowerDecoder2, actually Decode2Execute1Type |
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2020-06-11 |
Luke Kenneth Casso... | read and write version of get_sim_xer_ca are different |
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2020-06-11 |
Luke Kenneth Casso... | rename get_sim_cr_a to get_wr_sim_cr_a for now |
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2020-06-10 |
Luke Kenneth Casso... | use sim-get helpers in ALU input fetch |
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2020-06-10 |
Luke Kenneth Casso... | continue ALUHelpers check alu outputs code-morph |
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2020-06-10 |
Luke Kenneth Casso... | code-morph ALU output test check phase |
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2020-06-10 |
Luke Kenneth Casso... | code-munge test_pipe_caller for ALU, |
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2020-06-08 |
Luke Kenneth Casso... | more verbose debug information tracking down SO/OV... |
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2020-06-08 |
Luke Kenneth Casso... | set only the SO bit as sticky, not the OV flags as... |
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2020-06-08 |
Luke Kenneth Casso... | clarify using microwatt calc_ov function. |
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2020-06-08 |
Luke Kenneth Casso... | added check which shows that OV32 in "adde." is not... |
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2020-06-07 |
Luke Kenneth Casso... | add extra missing args to ISA setup in alu test_pipe_caller |
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2020-06-06 |
Luke Kenneth Casso... | update stage docstring |
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2020-06-06 |
Luke Kenneth Casso... | code-munge |
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2020-06-06 |
Luke Kenneth Casso... | remove unneeded imports |
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2020-06-06 |
Luke Kenneth Casso... | noticed the regular pattern in all pipe_data.py (regspecs). |
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2020-06-04 |
Luke Kenneth Casso... | no global variables in test suites |
tree | commitdiff |
2020-06-04 |
Luke Kenneth Casso... | use common TestCase in alu |
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2020-06-04 |
Luke Kenneth Casso... | use copy of FHDLTestCase |
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2020-06-03 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2020-06-03 |
Luke Kenneth Casso... | reorganise ALU tests, move get_cu_inputs function to... |
tree | commitdiff |
2020-06-03 |
Luke Kenneth Casso... | attempt to make carry-in and overflow-enable optional... |
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2020-06-03 |
Luke Kenneth Casso... | remove rdflags in pipe_data.py (redundant) |
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2020-06-02 |
Luke Kenneth Casso... | rename regspecs to give a consistent naming scheme |
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2020-06-01 |
Luke Kenneth Casso... | okaaay add a "rdflags" function which obtains the yes... |
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2020-06-01 |
Luke Kenneth Casso... | RS moved to port 1 (from port 3), remove need in ALU... |
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2020-05-31 |
Luke Kenneth Casso... | clarify |
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2020-05-31 |
Luke Kenneth Casso... | OP_CMPEQB also requesting change of output reg (stop... |
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2020-05-31 |
Luke Kenneth Casso... | OP_CMP is requesting a change of the output register... |
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2020-05-31 |
Luke Kenneth Casso... | still investigating |
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2020-05-31 |
Luke Kenneth Casso... | start with zero, try not to compare against 9 bytes... |
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2020-05-31 |
Luke Kenneth Casso... | add in more CR debug statements |
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2020-05-31 |
Luke Kenneth Casso... | remove commented-out vars from ALU input record |
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2020-05-31 |
Luke Kenneth Casso... | add write_cr to ALU record subset |
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2020-05-30 |
Luke Kenneth Casso... | select CR0 write out only when RC=1 |
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2020-05-28 |
Luke Kenneth Casso... | remove trick of not setting SO |
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2020-05-27 |
Luke Kenneth Casso... | LogicalOutputData does not need XER.so |
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2020-05-27 |
Luke Kenneth Casso... | comments |
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2020-05-27 |
Luke Kenneth Casso... | check cr0, ov and ca ok signals in ALU main_stage proof |
tree | commitdiff |
2020-05-27 |
Luke Kenneth Casso... | add carry-out, overflow and cr0 ok setting in ALU main_... |
tree | commitdiff |
2020-05-27 |
Luke Kenneth Casso... | add links to bugreports into ALu formal proof as well |
tree | commitdiff |
2020-05-27 |
Luke Kenneth Casso... | add links to bugreports into alu output stage proof |
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2020-05-27 |
Michael Nolan | Fix bug in alu main stage proof |
tree | commitdiff |
2020-05-24 |
Luke Kenneth Casso... | convert ALU to output Data on int reg |
tree | commitdiff |
2020-05-24 |
Luke Kenneth Casso... | cleanup/code-munge on ALU main stage proof |
tree | commitdiff |
2020-05-24 |
Luke Kenneth Casso... | error in alu output stage formal proof setup |
tree | commitdiff |
2020-05-24 |
Luke Kenneth Casso... | output registers need to be Data type (consistently) |
tree | commitdiff |
2020-05-23 |
Luke Kenneth Casso... | remove unneeded imports |
tree | commitdiff |
2020-05-22 |
Luke Kenneth Casso... | split out Logical Input and Output stages to common... |
tree | commitdiff |
2020-05-22 |
Luke Kenneth Casso... | covert ALU FU to CommonInputStage |
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2020-05-21 |
Luke Kenneth Casso... | comment CompALUOpSubset, data_len is actually used... |
tree | commitdiff |
2020-05-21 |
Luke Kenneth Casso... | add zero_a flag to CompALUOpSubset |
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2020-05-21 |
Luke Kenneth Casso... | whitespace/shuffle |
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2020-05-21 |
Luke Kenneth Casso... | move common functionality between PipeSpecs to soc... |
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2020-05-21 |
Luke Kenneth Casso... | move FU IntegerData to directory below |
tree | commitdiff |
2020-05-21 |
Luke Kenneth Casso... | convert to individual PipeSpecs for each pipeline |
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2020-05-21 |
Luke Kenneth Casso... | add regspec to ALUPipeSpec |
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2020-05-20 |
Luke Kenneth Casso... | add register specs to pipeline in/out so that they... |
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2020-05-20 |
Michael Nolan | Use overflow definition from microwatt |
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2020-05-20 |
Michael Nolan | Add overflow handling and proof |
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2020-05-20 |
Michael Nolan | Fix bug introduced in rebase |
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2020-05-20 |
Luke Kenneth Casso... | formal proof rename on XER flags |
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2020-05-20 |
Luke Kenneth Casso... | update to new names for XER fields |
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2020-05-20 |
Luke Kenneth Casso... | normalise XER regs carry/32 and SO |
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2020-05-20 |
Luke Kenneth Casso... | whitespace, rename ilang to alu_main_stage.il |
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2020-05-20 |
Luke Kenneth Casso... | i seem to like short names that happen to make things... |
tree | commitdiff |
2020-05-20 |
Michael Nolan | Add proof for OP_CMP and OP_CMPEQB |
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2020-05-20 |
Michael Nolan | Add proof for OP_EXTS |
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2020-05-20 |
Michael Nolan | Add 32 bit carry handling to alu |
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2020-05-20 |
Luke Kenneth Casso... | output ilang for ALU to unique file |
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2020-05-20 |
Luke Kenneth Casso... | use nmutil exts helper in ALU OP_EXTS |
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2020-05-20 |
Luke Kenneth Casso... | minor code-munge, use shorter names |
tree | commitdiff |
2020-05-20 |
Luke Kenneth Casso... | convert alu output to use Data for XER and CR0 |
tree | commitdiff |
2020-05-19 |
Michael Nolan | Handle carry out in alu |
tree | commitdiff |
2020-05-19 |
Luke Kenneth Casso... | 32-bit testing of output for CR0 conditions |
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2020-05-18 |
Luke Kenneth Casso... | mass-rename of modules to soc.fu.* |
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2020-05-18 |
Luke Kenneth Casso... | rename pipe to fu |
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