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litex/florent/versa_ecp5.py add arg --fpga [versa_ecp5|ulx3s85f] default
[soc.git] / src / soc / litex / florent / libresoc /
2020-10-06 Luke Kenneth Casso... add sdr bypass routing via JTAG boundary scan tree | commitdiff
2020-10-04 Luke Kenneth Casso... significant reorg of the litex pinspecs to use pinmux... tree | commitdiff
2020-10-04 Luke Kenneth Casso... remove ls180io import tree | commitdiff
2020-10-04 Luke Kenneth Casso... move ls180io.py back into ls180.py tree | commitdiff
2020-10-03 Luke Kenneth Casso... allow i2c to be routed via JTAG tree | commitdiff
2020-10-03 Luke Kenneth Casso... nope. put it back and connect to platform pads in... tree | commitdiff
2020-10-03 Luke Kenneth Casso... move iopad litex creation to ls180soc.py tree | commitdiff
2020-10-01 Luke Kenneth Casso... add clksel, pll to ls180 tree | commitdiff
2020-09-30 Luke Kenneth Casso... add I2C into ls180 tree | commitdiff
2020-09-30 Luke Kenneth Casso... add ASIC version of I2C Master tree | commitdiff
2020-09-28 Luke Kenneth Casso... reduce not-connected IO pins tree | commitdiff
2020-09-28 Luke Kenneth Casso... lots of sorting out iopads tree | commitdiff
2020-09-26 Luke Kenneth Casso... add ls180io.py tree | commitdiff
2020-09-26 Luke Kenneth Casso... reduce sdram pins to smaller address and only 1 cs_n tree | commitdiff
2020-09-26 Luke Kenneth Casso... only enable pads connections for ls180 for now tree | commitdiff
2020-09-24 Luke Kenneth Casso... do not have to use uart_litex gpio_litex names tree | commitdiff
2020-09-24 Luke Kenneth Casso... enable GPIO pads through C4M JTAG tree | commitdiff
2020-09-24 Luke Kenneth Casso... c4m iopad integration working tree | commitdiff
2020-09-23 Luke Kenneth Casso... cs_n and cke in sdram need to match in length tree | commitdiff
2020-09-23 Luke Kenneth Casso... change litex sdram pinouts to ASIC type tree | commitdiff
2020-09-23 Luke Kenneth Casso... redo litex SDCard to send out data/cmd o/i/en pins tree | commitdiff
2020-09-23 Luke Kenneth Casso... sort out GPIO with i/o/oe in ls180 tree | commitdiff
2020-09-23 Luke Kenneth Casso... attempt GPIO bi-directional tree | commitdiff
2020-09-23 Luke Kenneth Casso... add I2C master to ls180 tree | commitdiff
2020-09-22 Luke Kenneth Casso... add 2 PWMs (quick, easy to do) tree | commitdiff
2020-09-22 Luke Kenneth Casso... add jtagremote to litex sim, add new "variant" to core... tree | commitdiff
2020-09-22 Luke Kenneth Casso... add jtag wishbone and jtag ports to libresoc litex... tree | commitdiff
2020-09-22 Luke Kenneth Casso... add JTAG IOpads and rename rst to sys_rst tree | commitdiff
2020-09-22 Luke Kenneth Casso... add similar platforms to ls180.py tree | commitdiff
2020-09-19 Luke Kenneth Casso... add pc_o not connected tree | commitdiff
2020-09-19 Luke Kenneth Casso... urk. wishbone slave devices declared incorrectly (I... semi_working_ecp5 tree | commitdiff
2020-09-19 Luke Kenneth Casso... add (disabled) tri-state GPIO tree | commitdiff
2020-09-19 Luke Kenneth Casso... remove the gpio peripheral which was previously hard... tree | commitdiff
2020-09-19 Luke Kenneth Casso... add 3x EINTs to ls180soc tree | commitdiff
2020-09-18 Luke Kenneth Casso... add SPI, sdcard, preliminary GPIO to ls180 pinouts tree | commitdiff
2020-09-18 Luke Kenneth Casso... argh got fed up trying to shoe-horn into sim.py tree | commitdiff
2020-09-16 Luke Kenneth Casso... make a start on LS180 platform tree | commitdiff
2020-09-16 Cole Poirieradd template file/starting point (copy of litex/boards... tree | commitdiff
2020-09-05 Luke Kenneth Casso... move GPIO IRQ to 15 to match microwatt modifications tree | commitdiff
2020-09-05 Luke Kenneth Casso... XICS addresses in words: divide by 4 tree | commitdiff
2020-09-05 Luke Kenneth Casso... increase wishbone address width to 29 for xics and... tree | commitdiff
2020-09-05 Luke Kenneth Casso... add simple GPIO wishbone bus to litex sim.py tree | commitdiff
2020-09-04 Luke Kenneth Casso... add XICS memory regions, shrink litex CSR memmap size... tree | commitdiff
2020-09-04 Luke Kenneth Casso... adding XICS wb slave devices to litex sim tree | commitdiff
2020-08-25 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc tree | commitdiff
2020-08-25 Luke Kenneth Casso... add way to capture CR from DMI in litex sim tree | commitdiff
2020-08-21 Luke Kenneth Casso... get litex sim enabled with 32-bit wishbone bus tree | commitdiff
2020-08-05 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org... tree | commitdiff
2020-08-05 Luke Kenneth Casso... rename ibus/dbus (shorten) tree | commitdiff
2020-08-04 Luke Kenneth Casso... add DMI debug interface to libresoc litex sim tree | commitdiff
2020-08-04 Luke Kenneth Casso... more remove wildcard imports tree | commitdiff
2020-08-04 Luke Kenneth Casso... adding litex sim experimentation. tree | commitdiff