2020-07-22 |
Jacob Lifshay | working on fsm |
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2020-07-22 |
Jacob Lifshay | Merge remote-tracking branch 'origin/master' |
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2020-07-22 |
Jacob Lifshay | format code |
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2020-07-22 |
Luke Kenneth Casso... | re-add CRG (clock reset generator) |
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2020-07-22 |
Luke Kenneth Casso... | missing ports from issuer, when doing verilog |
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2020-07-22 |
Luke Kenneth Casso... | add clock domain using snippet taken from random file |
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2020-07-22 |
Luke Kenneth Casso... | cleanup in litex core.py |
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2020-07-22 |
Luke Kenneth Casso... | update comments |
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2020-07-22 |
Luke Kenneth Casso... | add dummy irq set/get |
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2020-07-22 |
Luke Kenneth Casso... | add boot-helper.S etc from microwatt litex core |
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2020-07-22 |
Luke Kenneth Casso... | set additional MSR bits according to v3.0B spec when... |
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2020-07-22 |
Luke Kenneth Casso... | use (new) MSRb and PIb which has auto-bigendian numbers |
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2020-07-22 |
Luke Kenneth Casso... | sigh, auto-create some little/big-endian classes for... |
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2020-07-22 |
Luke Kenneth Casso... | missed import of Builder, set cpu_type to "None" tempor... |
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2020-07-22 |
Luke Kenneth Casso... | begin converting litex sim to libre-soc |
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2020-07-22 |
Luke Kenneth Casso... | whoops forgot field accessor |
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2020-07-22 |
Luke Kenneth Casso... | do not use wildcard import |
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2020-07-22 |
Luke Kenneth Casso... | start from vexriscv sim.py from |
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2020-07-22 |
Luke Kenneth Casso... | correct syntax error |
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2020-07-22 |
Luke Kenneth Casso... | first version of litex core (to be submitted upstream... |
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2020-07-22 |
Luke Kenneth Casso... | whoops typo, 63-start not 3-start (doh) |
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2020-07-22 |
Luke Kenneth Casso... | field number ordering wrong way round? |
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2020-07-22 |
Luke Kenneth Casso... | syntax error |
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2020-07-22 |
Luke Kenneth Casso... | review trap main_stage.py modifications: we are not... |
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2020-07-22 |
Luke Kenneth Casso... | comments, add page spec numbers for branch ops into... |
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2020-07-22 |
Luke Kenneth Casso... | add comment headings with spec page numbers |
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2020-07-22 |
Luke Kenneth Casso... | comment on op.insn ordering |
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2020-07-22 |
Luke Kenneth Casso... | code-shuffle, add comments |
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2020-07-22 |
Luke Kenneth Casso... | add TT.size and use it in PowerDecoder and trap input... |
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2020-07-22 |
Luke Kenneth Casso... | inline comments in trap proof |
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2020-07-22 |
Luke Kenneth Casso... | note that traptype MUST increase in bitwidth correspond... |
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2020-07-22 |
Luke Kenneth Casso... | fix branch main_stage proof, add ctr 32-bit, fix BCREG |
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2020-07-22 |
Luke Kenneth Casso... | rework branch proof to use br_input_record |
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2020-07-22 |
Luke Kenneth Casso... | update README for pipe_data.py |
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2020-07-22 |
Luke Kenneth Casso... | reduce number of FastRegs read ports |
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2020-07-22 |
Luke Kenneth Casso... | comments on what goes into CommonPipeSpec |
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2020-07-22 |
Samuel A. Falvo II | Complete FV properties for OP_TRAP instructions. |
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2020-07-22 |
Samuel A. Falvo II | PEP8 compliance |
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2020-07-22 |
Jacob Lifshay | working on FSMDivCoreStage |
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2020-07-22 |
Jacob Lifshay | fix test_div_state_fsm |
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2020-07-21 |
Samuel A. Falvo II | Completed SC FV properties |
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2020-07-21 |
Samuel A. Falvo II | Refine properties to comply with spec |
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2020-07-21 |
Samuel A. Falvo II | Fix where msr_i gets its value from |
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2020-07-21 |
Samuel A. Falvo II | Merge in recent updates to TRAP FV properties. |
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2020-07-21 |
Luke Kenneth Casso... | convert branch pipeline to use msr/cia as immediates |
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2020-07-21 |
Luke Kenneth Casso... | put set_msr and set_cia back in for now |
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2020-07-21 |
Luke Kenneth Casso... | interesting bug in test_compunit.py when there are... |
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2020-07-21 |
Luke Kenneth Casso... | testing if MultiCompUnit can handle no input regs ... |
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2020-07-21 |
Luke Kenneth Casso... | disable cxxsim for now |
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2020-07-21 |
Luke Kenneth Casso... | move cia and msr to trap input record |
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2020-07-21 |
Luke Kenneth Casso... | set ISACaller.msr rather than namespace[MSR] |
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2020-07-21 |
Luke Kenneth Casso... | when running an exception (trap) after "reset" must... |
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2020-07-21 |
Luke Kenneth Casso... | spurious imports of FHDLTestCase, should be from nmutil |
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2020-07-21 |
Luke Kenneth Casso... | whitespace |
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2020-07-21 |
Luke Kenneth Casso... | add PC (CIA) to PowerDecode2 "state" for passing into... |
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2020-07-21 |
Luke Kenneth Casso... | add msr exception bits setting function in hardware |
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2020-07-21 |
Luke Kenneth Casso... | make cxxsim optional and print warning |
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2020-07-21 |
Luke Kenneth Casso... | corrections to trap proof see |
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2020-07-21 |
Luke Kenneth Casso... | use alias for msr_i in trap proof |
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2020-07-21 |
Luke Kenneth Casso... | correct trap spec page interrupt ref |
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2020-07-20 |
Samuel A. Falvo II | Rework SC properties to conform to style |
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2020-07-20 |
Samuel A. Falvo II | Formal properties for RFID. |
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2020-07-20 |
Cesar Strauss | Document the move of sdir from data_i to op. |
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2020-07-20 |
Cesar Strauss | Remove extra yield from test case. |
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2020-07-19 |
Luke Kenneth Casso... | do not start core in terminated mode |
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2020-07-19 |
Luke Kenneth Casso... | explicitly set up a pc_i_ok signal in test_microwatt.py |
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2020-07-19 |
Luke Kenneth Casso... | expose core_stop_i to outside as well |
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2020-07-19 |
Luke Kenneth Casso... | set go_insn_i to non-resetless |
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2020-07-19 |
Luke Kenneth Casso... | add issuer verilog generator |
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2020-07-19 |
Luke Kenneth Casso... | update to expose signals at top-level of issuer |
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2020-07-19 |
Luke Kenneth Casso... | convert compalu multi test to Simulator() (was run_simu... |
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2020-07-19 |
Luke Kenneth Casso... | convert compalu multi test to Simulator() (was run_simu... |
tree | commitdiff |
2020-07-19 |
Luke Kenneth Casso... | use same write_vcd for cxxsim as pysim |
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2020-07-19 |
Luke Kenneth Casso... | fix bug in alu_fsm.py found by cxxsim: missing one... |
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2020-07-19 |
Luke Kenneth Casso... | add some CompUnit demo tests of the alu_fsm example |
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2020-07-19 |
Luke Kenneth Casso... | move sdir to CompFSMOpSubset in alu_fsm example |
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2020-07-19 |
Luke Kenneth Casso... | add CompFSMOpSubset, also change dir to sdir |
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2020-07-19 |
Luke Kenneth Casso... | remove unneeded import |
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2020-07-19 |
Luke Kenneth Casso... | if nmigen.sim.pysim import fails use nmigen.back.pysim |
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2020-07-19 |
Luke Kenneth Casso... | use iocontrol PrevControl / NextControl instead of... |
tree | commitdiff |
2020-07-19 |
Luke Kenneth Casso... | add DivTestCase to test_issuer.py (commented out for... |
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2020-07-19 |
Cesar Strauss | Implement control path and unit test. |
tree | commitdiff |
2020-07-18 |
Luke Kenneth Casso... | worked out that DivPipeSpec can be given a default... |
tree | commitdiff |
2020-07-18 |
Luke Kenneth Casso... | missing conversion of DIV to Div |
tree | commitdiff |
2020-07-18 |
Luke Kenneth Casso... | add option to generate verilog |
tree | commitdiff |
2020-07-18 |
Luke Kenneth Casso... | whoops use slice not range |
tree | commitdiff |
2020-07-18 |
Luke Kenneth Casso... | syntax error |
tree | commitdiff |
2020-07-18 |
Cesar Strauss | Implement the Shifter data path |
tree | commitdiff |
2020-07-18 |
Cesar Strauss | Document move of the next port data |
tree | commitdiff |
2020-07-18 |
Luke Kenneth Casso... | add SR latch cxxrtl backend demo |
tree | commitdiff |
2020-07-18 |
Luke Kenneth Casso... | add comment and copy of pseudo-code for OP_RFID into... |
tree | commitdiff |
2020-07-18 |
Luke Kenneth Casso... | review of OP_RFID showed up some errors |
tree | commitdiff |
2020-07-18 |
Luke Kenneth Casso... | corrections to trap main_stage.py OP_RFID according... |
tree | commitdiff |
2020-07-18 |
Samuel A. Falvo II | WIP: FV failing for unknown reasons. |
tree | commitdiff |
2020-07-18 |
Jacob Lifshay | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2020-07-18 |
Jacob Lifshay | add div fsm core (`DivState*`) with tests |
tree | commitdiff |
2020-07-18 |
Samuel A. Falvo II | Failing test: fast1/fast2 vs srr0/srr1? on trap pipe |
tree | commitdiff |
2020-07-18 |
Samuel A. Falvo II | forgot to clean up workspace in source |
tree | commitdiff |
2020-07-18 |
Samuel A. Falvo II | FV props for SC instruction |
tree | commitdiff |
2020-07-17 |
Samuel A. Falvo II | First FV property for trap unit |
tree | commitdiff |
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