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correct trap spec page interrupt ref
[soc.git]
/
src
/
2020-07-21
Luke Kenneth Casso...
correct trap spec page interrupt ref
tree
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commitdiff
2020-07-20
Samuel A. Falvo II
Rework SC properties to conform to style
tree
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commitdiff
2020-07-20
Samuel A. Falvo II
Formal properties for RFID.
tree
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commitdiff
2020-07-20
Cesar Strauss
Document the move of sdir from data_i to op.
tree
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commitdiff
2020-07-20
Cesar Strauss
Remove extra yield from test case.
tree
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commitdiff
2020-07-19
Luke Kenneth Casso...
do not start core in terminated mode
tree
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commitdiff
2020-07-19
Luke Kenneth Casso...
explicitly set up a pc_i_ok signal in test_microwatt.py
tree
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commitdiff
2020-07-19
Luke Kenneth Casso...
expose core_stop_i to outside as well
tree
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commitdiff
2020-07-19
Luke Kenneth Casso...
set go_insn_i to non-resetless
tree
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commitdiff
2020-07-19
Luke Kenneth Casso...
add issuer verilog generator
tree
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commitdiff
2020-07-19
Luke Kenneth Casso...
update to expose signals at top-level of issuer
tree
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commitdiff
2020-07-19
Luke Kenneth Casso...
convert compalu multi test to Simulator() (was run_simu...
tree
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commitdiff
2020-07-19
Luke Kenneth Casso...
convert compalu multi test to Simulator() (was run_simu...
tree
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commitdiff
2020-07-19
Luke Kenneth Casso...
use same write_vcd for cxxsim as pysim
tree
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commitdiff
2020-07-19
Luke Kenneth Casso...
fix bug in alu_fsm.py found by cxxsim: missing one...
tree
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commitdiff
2020-07-19
Luke Kenneth Casso...
add some CompUnit demo tests of the alu_fsm example
tree
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commitdiff
2020-07-19
Luke Kenneth Casso...
move sdir to CompFSMOpSubset in alu_fsm example
tree
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commitdiff
2020-07-19
Luke Kenneth Casso...
add CompFSMOpSubset, also change dir to sdir
tree
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commitdiff
2020-07-19
Luke Kenneth Casso...
remove unneeded import
tree
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commitdiff
2020-07-19
Luke Kenneth Casso...
if nmigen.sim.pysim import fails use nmigen.back.pysim
tree
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commitdiff
2020-07-19
Luke Kenneth Casso...
use iocontrol PrevControl / NextControl instead of...
tree
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commitdiff
2020-07-19
Luke Kenneth Casso...
add DivTestCase to test_issuer.py (commented out for...
tree
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commitdiff
2020-07-19
Cesar Strauss
Implement control path and unit test.
tree
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commitdiff
2020-07-18
Luke Kenneth Casso...
worked out that DivPipeSpec can be given a default...
tree
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commitdiff
2020-07-18
Luke Kenneth Casso...
missing conversion of DIV to Div
tree
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commitdiff
2020-07-18
Luke Kenneth Casso...
add option to generate verilog
tree
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commitdiff
2020-07-18
Luke Kenneth Casso...
whoops use slice not range
tree
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commitdiff
2020-07-18
Luke Kenneth Casso...
syntax error
tree
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commitdiff
2020-07-18
Cesar Strauss
Implement the Shifter data path
tree
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commitdiff
2020-07-18
Cesar Strauss
Document move of the next port data
tree
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commitdiff
2020-07-18
Luke Kenneth Casso...
add SR latch cxxrtl backend demo
tree
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commitdiff
2020-07-18
Luke Kenneth Casso...
add comment and copy of pseudo-code for OP_RFID into...
tree
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commitdiff
2020-07-18
Luke Kenneth Casso...
review of OP_RFID showed up some errors
tree
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commitdiff
2020-07-18
Luke Kenneth Casso...
corrections to trap main_stage.py OP_RFID according...
tree
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commitdiff
2020-07-18
Samuel A. Falvo II
WIP: FV failing for unknown reasons.
tree
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commitdiff
2020-07-18
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
tree
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commitdiff
2020-07-18
Jacob Lifshay
add div fsm core (`DivState*`) with tests
tree
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commitdiff
2020-07-18
Samuel A. Falvo II
Failing test: fast1/fast2 vs srr0/srr1? on trap pipe
tree
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commitdiff
2020-07-18
Samuel A. Falvo II
forgot to clean up workspace in source
tree
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commitdiff
2020-07-18
Samuel A. Falvo II
FV props for SC instruction
tree
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commitdiff
2020-07-17
Samuel A. Falvo II
First FV property for trap unit
tree
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commitdiff
2020-07-17
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
tree
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commitdiff
2020-07-17
Jacob Lifshay
start adding FSMDivCore*
tree
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commitdiff
2020-07-17
Luke Kenneth Casso...
comment explaining why not to call self.trap in PowerDe...
tree
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commitdiff
2020-07-17
Luke Kenneth Casso...
likewise cut across latest Minerva loadstore with line...
tree
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commitdiff
2020-07-17
Luke Kenneth Casso...
sigh easier to just do a line-for-line comparison of...
tree
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commitdiff
2020-07-17
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
tree
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commitdiff
2020-07-17
Luke Kenneth Casso...
port minerva cache fixes
tree
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commitdiff
2020-07-17
Luke Kenneth Casso...
forward-port minerva loadstore bugfix
tree
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commitdiff
2020-07-17
Luke Kenneth Casso...
comments
tree
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commitdiff
2020-07-17
Luke Kenneth Casso...
whitespace
tree
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commitdiff
2020-07-17
Luke Kenneth Casso...
use convenience vars in spr proof
tree
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commitdiff
2020-07-17
Samuel A. Falvo II
Flesh out SPR-related FV properties.
tree
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commitdiff
2020-07-17
Luke Kenneth Casso...
whitespace
tree
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commitdiff
2020-07-17
Luke Kenneth Casso...
whitespace
tree
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commitdiff
2020-07-17
Jacob Lifshay
add simulation-only division core using nmigen div...
tree
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commitdiff
2020-07-17
Jacob Lifshay
rename DIV->Div to be consistent
tree
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commitdiff
2020-07-17
Jacob Lifshay
format div code
tree
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commitdiff
2020-07-17
Jacob Lifshay
add missing fixedldstcache.py to .gitignore
tree
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commitdiff
2020-07-16
Luke Kenneth Casso...
whoops tried doing mtspr priv, it failed but failed...
div_pipeline
tree
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commitdiff
2020-07-16
Luke Kenneth Casso...
get shiftrot compunit working
tree
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commitdiff
2020-07-16
Luke Kenneth Casso...
more tidyup on use of CompOpSubsetBase
tree
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commitdiff
2020-07-16
Luke Kenneth Casso...
use CompOpSubsetBase in ldst record
tree
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commitdiff
2020-07-16
Luke Kenneth Casso...
sigh, bug in sprset.patch
tree
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commitdiff
2020-07-16
Luke Kenneth Casso...
update cr input record to use new CompOpSubsetBase
tree
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commitdiff
2020-07-16
Luke Kenneth Casso...
add regression test on setb simulator error
tree
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commitdiff
2020-07-16
Luke Kenneth Casso...
use CompOpSubsetBase class in Branch op record
tree
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commitdiff
2020-07-16
Luke Kenneth Casso...
get branch compunit working (missing bigendian arg)
tree
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commitdiff
2020-07-16
Luke Kenneth Casso...
get trap compunit test working, adding bigendian and msr
tree
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commitdiff
2020-07-16
Luke Kenneth Casso...
add mfmsr trap tests
tree
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commitdiff
2020-07-15
Luke Kenneth Casso...
use new CompOpSubsetBase in trap
tree
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commitdiff
2020-07-15
Luke Kenneth Casso...
remove unneeded comment in trap msin stage
tree
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commitdiff
2020-07-15
Luke Kenneth Casso...
remove unneeded comment in trap pipe_data
tree
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commitdiff
2020-07-15
Luke Kenneth Casso...
document branch pipeline relationship with PowerDecode2
tree
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commitdiff
2020-07-15
Luke Kenneth Casso...
simplify instr_is_priv
tree
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commitdiff
2020-07-15
Luke Kenneth Casso...
move traptype to soc.consts
tree
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commitdiff
2020-07-15
Luke Kenneth Casso...
add better comments on mul overflow
tree
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commitdiff
2020-07-15
Luke Kenneth Casso...
test privileged rfid call
tree
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commitdiff
2020-07-15
Luke Kenneth Casso...
spelling error
tree
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commitdiff
2020-07-15
Luke Kenneth Casso...
range of testing overflow was incorrect in mul
tree
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commitdiff
2020-07-15
Luke Kenneth Casso...
set MSR up properly for privileged mtmsr test
tree
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commitdiff
2020-07-15
Luke Kenneth Casso...
whoops forgot to update PC after trap in ISACaller
tree
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commitdiff
2020-07-15
Luke Kenneth Casso...
move priv test to above illegal/trap test
tree
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commitdiff
2020-07-15
Luke Kenneth Casso...
comments on IntegerData class
tree
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commitdiff
2020-07-15
Luke Kenneth Casso...
import PipeContext not FPPipeContext
tree
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commitdiff
2020-07-15
Luke Kenneth Casso...
minor reorg on PowerDecoder2, use switch/case rather...
tree
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commitdiff
2020-07-15
Luke Kenneth Casso...
comments on SPRmap done in PowerDecode2
tree
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commitdiff
2020-07-15
Luke Kenneth Casso...
comments on SPRmap done in PowerDecode2
tree
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commitdiff
2020-07-15
Luke Kenneth Casso...
use case statement in PowerDecode2
tree
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commitdiff
2020-07-15
Luke Kenneth Casso...
select RA based on LDSTMode.update in PowerDecode2
tree
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commitdiff
2020-07-15
Luke Kenneth Casso...
add cache cx to LDSTMode
tree
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commitdiff
2020-07-15
Luke Kenneth Casso...
remove unused class XerBits
tree
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commitdiff
2020-07-15
Luke Kenneth Casso...
use Record Assert and also check muxid
tree
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commitdiff
2020-07-15
Luke Kenneth Casso...
no need to check individual port members, just check...
tree
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commitdiff
2020-07-14
Luke Kenneth Casso...
cookie-cut setup from alu proof_main_stage.py
tree
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commitdiff
2020-07-14
Luke Kenneth Casso...
reduce code size by using CompOpSubsetBase for ALU...
tree
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commitdiff
2020-07-14
Luke Kenneth Casso...
split out CompOpSubsetBase (meaning to do for a while)
tree
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commitdiff
2020-07-14
Luke Kenneth Casso...
update docstrings
tree
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commitdiff
2020-07-14
Luke Kenneth Casso...
adding MSR.PR unit test intended to activate privileged...
tree
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commitdiff
2020-07-14
Luke Kenneth Casso...
attempting to access self.msr directly
tree
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commitdiff
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