Revert "remove fixedlogical.patch - added gprs to PowerParser p_atom_name"
[soc.git] / src /
2020-06-07 Luke Kenneth Casso... Revert "remove fixedlogical.patch - added gprs to Power...
2020-06-07 Luke Kenneth Casso... Revert "add gprs to PowerParser write_regs in p_atom_name"
2020-06-07 Luke Kenneth Casso... add extra missing args to ISA setup in alu test_pipe_caller
2020-06-07 Luke Kenneth Casso... if referred to through GPR (GPR[RA]), add to read_regs...
2020-06-07 Luke Kenneth Casso... add gprs to PowerParser write_regs in p_atom_name
2020-06-07 Luke Kenneth Casso... add missing args to ISA
2020-06-07 Luke Kenneth Casso... remove fixedlogical.patch - added gprs to PowerParser...
2020-06-07 Luke Kenneth Casso... docstring on caller.py inject() decorator
2020-06-07 Luke Kenneth Casso... add TRAP function, stub
2020-06-07 Luke Kenneth Casso... add MSR to simulator context
2020-06-07 Luke Kenneth Casso... move MSR_PR checking to separate functiong
2020-06-07 colepoirierFix missing 'comb +='
2020-06-06 Luke Kenneth Casso... experimenting with setting up and testing memory
2020-06-06 Luke Kenneth Casso... expand regwid to 64 in l0_cache test
2020-06-06 Luke Kenneth Casso... work out how to initialise memory directly
2020-06-06 Luke Kenneth Casso... initialise L0 Memory from simulator memory
2020-06-06 Luke Kenneth Casso... wait a little for wr.rel to activate if wrmask is active
2020-06-06 Luke Kenneth Casso... missing test.mem arg for ISA in test_core
2020-06-06 Luke Kenneth Casso... allow Mem initialisation in ISACaller
2020-06-06 Luke Kenneth Casso... shift-mask in Simulator Mem class not quite right
2020-06-06 Luke Kenneth Casso... write-mask made from LD and Update mode (for data_o...
2020-06-06 Luke Kenneth Casso... allow Mem in Simulator to be initialised
2020-06-06 Luke Kenneth Casso... use name of unit to write simulator/vcd file
2020-06-06 Luke Kenneth Casso... LDSTCompUnit test data structures linked up, starting...
2020-06-06 Luke Kenneth Casso... allow CompLDSTOpSubset to be passed through to LDSTCompUnit
2020-06-06 Luke Kenneth Casso... set up LDSTCompUnit using regspec
2020-06-06 Luke Kenneth Casso... add extra bugreport link
2020-06-06 Luke Kenneth Casso... whitespace
2020-06-06 Luke Kenneth Casso... whitespace indentation
2020-06-06 Luke Kenneth Casso... add special-case LDSTFunctionUnit
2020-06-06 Luke Kenneth Casso... whoops dest%d_o not dest%d_i
2020-06-06 Luke Kenneth Casso... add beginnings of LDST compunit test
2020-06-06 Luke Kenneth Casso... whitespace
2020-06-06 Luke Kenneth Casso... whitespace / code-munge
2020-06-06 Luke Kenneth Casso... comments / whitespace
2020-06-06 Luke Kenneth Casso... update stage docstring
2020-06-06 Luke Kenneth Casso... code-munge
2020-06-06 Luke Kenneth Casso... remove unneeded imports
2020-06-06 Luke Kenneth Casso... noticed the regular pattern in all pipe_data.py (regspecs).
2020-06-05 Luke Kenneth Casso... comment out CR assertion for now
2020-06-05 colepoirierAdded skeleton fu/trap/test/test_pipe_caller using
2020-06-05 colepoirierAdd trap_input_data.py for fu/trap, cookie-cut from
2020-06-05 Tobias Platenfix proof_datamerger (see 216#c56)
2020-06-05 Luke Kenneth Casso... update comments
2020-06-05 Luke Kenneth Casso... add comments and start of elaborate
2020-06-05 Luke Kenneth Casso... more comments
2020-06-05 Luke Kenneth Casso... more comments
2020-06-05 Luke Kenneth Casso... a_i not b_in
2020-06-05 Luke Kenneth Casso... add comments
2020-06-05 Luke Kenneth Casso... experimenting with CR, not quite right
2020-06-05 colepoirierMade small changes to fu/trap/main_stage to bring nmige...
2020-06-05 Tobias Platenimplement init function of DualPortSplitter
2020-06-05 Tobias Platenuncomment rtlil.convert in test_l0_cache that causes...
2020-06-05 Luke Kenneth Casso... whoops returning cr2 for cr3 regspec map
2020-06-05 Luke Kenneth Casso... name regfile ports by name not numerical position
2020-06-05 Luke Kenneth Casso... whoops connecting up CR in wrong order. fixing with...
2020-06-05 Luke Kenneth Casso... fix syntax errors and use correct FastRegs (SRR0/1...
2020-06-05 Luke Kenneth Casso... add TODO for MFSPR/MTSPR
2020-06-05 Luke Kenneth Casso... refer to srr0/1 not a/b
2020-06-05 Luke Kenneth Casso... add msr_copy function and use it in OP_TRAP, OP_RFID...
2020-06-05 Luke Kenneth Casso... set SRR0 in OP_SC
2020-06-05 Luke Kenneth Casso... add OP_RFID SRR0/SRR1 in PowerDecode2
2020-06-04 colepoirierUse a_i and b_i convenience variables instead of a...
2020-06-04 Luke Kenneth Casso... testing CRs after writing: not in the right bit-order
2020-06-04 Luke Kenneth Casso... remove unneeded code
2020-06-04 Luke Kenneth Casso... use common TestCase class in logical
2020-06-04 Luke Kenneth Casso... add branch test case to core
2020-06-04 Luke Kenneth Casso... no global variables in test suites
2020-06-04 Luke Kenneth Casso... sigh. because POWER. CR index inversion
2020-06-04 Luke Kenneth Casso... sigh. weirdness involving bit-inversion, inconsistency...
2020-06-04 Luke Kenneth Casso... no global variables in test suites
2020-06-04 Luke Kenneth Casso... add ShiftRot test case (works only because CRs are...
2020-06-04 Luke Kenneth Casso... add both logical and ALU test core
2020-06-04 Luke Kenneth Casso... no global variables in test suites
2020-06-04 Luke Kenneth Casso... no global variables in test suites
2020-06-04 Luke Kenneth Casso... no global variables in test suites
2020-06-04 Luke Kenneth Casso... whoops, docstring indentation
2020-06-04 Luke Kenneth Casso... add docstrings for read/write port connection
2020-06-04 Luke Kenneth Casso... move core code into separate functions, for clarity
2020-06-04 Luke Kenneth Casso... reduce amount of code in SelectableInt
2020-06-04 Luke Kenneth Casso... oops forgot to switch write-enable off
2020-06-04 Luke Kenneth Casso... comment clarify on core
2020-06-04 Luke Kenneth Casso... initialise XER from simulation
2020-06-04 Luke Kenneth Casso... messing with valid/busy signals in core test
2020-06-04 Luke Kenneth Casso... add extra argument (not used) to regfile.py
2020-06-04 Luke Kenneth Casso... hmmm sync-delay wport write and wen
2020-06-04 Luke Kenneth Casso... whitespace
2020-06-04 Luke Kenneth Casso... test actual reg values being produced in core test
2020-06-04 Luke Kenneth Casso... use common TestCase in branch
2020-06-04 Luke Kenneth Casso... use common TestCase in shift_rot
2020-06-04 Luke Kenneth Casso... use common TestCase in alu
2020-06-04 Luke Kenneth Casso... move TestCase to common location
2020-06-04 Luke Kenneth Casso... move reg setup to earlier in test
2020-06-04 Luke Kenneth Casso... comment out wrflag as it should already be in the fu...
2020-06-04 Luke Kenneth Casso... test against Logical (hard-coded change)
2020-06-04 Luke Kenneth Casso... add first cut at test core
2020-06-04 Luke Kenneth Casso... sync onto fu.go_wr_i otherwise a loop occurs
2020-06-04 Luke Kenneth Casso... add rdmask and issue/busy setting
2020-06-04 Luke Kenneth Casso... remove unneeded imports
2020-06-04 Luke Kenneth Casso... use copy of FHDLTestCase
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