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minor code-munge on SPR-to-FAST mapping
[soc.git] / src /
2020-09-06 Luke Kenneth Casso... minor code-munge on SPR-to-FAST mapping tree | commitdiff
2020-09-06 Luke Kenneth Casso... use with subTest in spr unit test tree | commitdiff
2020-09-06 Luke Kenneth Casso... redo generation of microwatt.v from litex tree | commitdiff
2020-09-06 Luke Kenneth Casso... add comments for DEC / TB tree | commitdiff
2020-09-06 Luke Kenneth Casso... add a DEC/TB FSM to TestIssuer tree | commitdiff
2020-09-06 Luke Kenneth Casso... move DEC and TB from StateRegs to FastRegs for several... tree | commitdiff
2020-09-06 Luke Kenneth Casso... add DEC SPR to CoreState and PowerDecoder, activate... tree | commitdiff
2020-09-06 Luke Kenneth Casso... add DEC and TB to State regfile tree | commitdiff
2020-09-06 Luke Kenneth Casso... add DEC/TB SPRs to spr pipeline tree | commitdiff
2020-09-05 Luke Kenneth Casso... add comments on MSR read tree | commitdiff
2020-09-05 Luke Kenneth Casso... move GPIO IRQ to 15 to match microwatt modifications tree | commitdiff
2020-09-05 Luke Kenneth Casso... hmmm XICS data being asserted on wb bus for too long tree | commitdiff
2020-09-05 Luke Kenneth Casso... argh missed a VHDL "&" translating to Cat tree | commitdiff
2020-09-05 Luke Kenneth Casso... reduce XICS address lookup by 2 bits tree | commitdiff
2020-09-05 Luke Kenneth Casso... MSR read in INSN_READ only occurs for 1 cycle tree | commitdiff
2020-09-05 Luke Kenneth Casso... sync on ICP eint tree | commitdiff
2020-09-05 Luke Kenneth Casso... connect XICS core irq to Decode2 eint tree | commitdiff
2020-09-05 Luke Kenneth Casso... whoops, combinatorial loop on pending_priority tree | commitdiff
2020-09-05 Luke Kenneth Casso... use stbcix in test tree | commitdiff
2020-09-05 Luke Kenneth Casso... XICS addresses in words: divide by 4 tree | commitdiff
2020-09-05 Luke Kenneth Casso... whoops, ICS in litex sim needs to be 0x1000 size region tree | commitdiff
2020-09-05 Luke Kenneth Casso... add lwzcix unit test tree | commitdiff
2020-09-05 Luke Kenneth Casso... increase wishbone address width to 29 for xics and... tree | commitdiff
2020-09-05 Luke Kenneth Casso... add simple GPIO wishbone bus to litex sim.py tree | commitdiff
2020-09-05 Luke Kenneth Casso... add stbcix and lwzcix to power_enum list tree | commitdiff
2020-09-05 Luke Kenneth Casso... add simple GPIO peripheral to verilog TestIssuer tree | commitdiff
2020-09-05 Luke Kenneth Casso... move wb read/write to separate util test library and... tree | commitdiff
2020-09-05 Luke Kenneth Casso... add simple wishbone GPIO peripheral tree | commitdiff
2020-09-05 Samuel A. Falvo IIAdd unit test replicating failing proof case tree | commitdiff
2020-09-04 Luke Kenneth Casso... add sld test with RB=64 to see what happens tree | commitdiff
2020-09-04 Luke Kenneth Casso... reduce CSR data width to 8 as an experiment tree | commitdiff
2020-09-04 Luke Kenneth Casso... add UART reserved IRQ @ 0 tree | commitdiff
2020-09-04 Luke Kenneth Casso... add XICS memory regions, shrink litex CSR memmap size... tree | commitdiff
2020-09-04 Luke Kenneth Casso... adding XICS wb slave devices to litex sim tree | commitdiff
2020-09-04 Luke Kenneth Casso... bring out XICS ICS interrupt levels so that they can... tree | commitdiff
2020-09-04 Luke Kenneth Casso... adding option to include XICS external interrupts. tree | commitdiff
2020-09-04 Luke Kenneth Casso... add means to run hello_world.bin under simulation tree | commitdiff
2020-09-04 Jacob Lifshayupdate to match refactored power-instruction-analyzer API tree | commitdiff
2020-09-03 Samuel A. Falvo IIProvide full name and email in copyright notice. tree | commitdiff
2020-09-03 Luke Kenneth Casso... do more on dcache conversion tree | commitdiff
2020-09-03 Luke Kenneth Casso... testing microwatt 3.bin (2.bin ok) tree | commitdiff
2020-09-02 Luke Kenneth Casso... when mtocrf FXM is 0, the CR has to be set to CR7 tree | commitdiff
2020-09-02 Luke Kenneth Casso... fix bug in cmpli (and cmplw) tree | commitdiff
2020-09-02 Luke Kenneth Casso... sign-extend lhax needs 16-64, separate from lwax which... tree | commitdiff
2020-09-02 Luke Kenneth Casso... add bc ctr regression test when CTR=0 and CTR=1 tree | commitdiff
2020-09-02 Luke Kenneth Casso... bug in carry32 handling in OP_CMP tree | commitdiff
2020-09-02 Luke Kenneth Casso... add cmpl regression test (one binary, one assembly) tree | commitdiff
2020-09-02 Luke Kenneth Casso... add cmpl microwatt 1.bin test, cmpl tree | commitdiff
2020-09-02 Luke Kenneth Casso... series of extensive modifications to fix long-standing... tree | commitdiff
2020-08-31 Luke Kenneth Casso... add XER to fastregs and "construct" it in mfspr/mtspr tree | commitdiff
2020-08-30 Luke Kenneth Casso... redo OP_CMP based on microwatt. L=1 had been ignored tree | commitdiff
2020-08-30 Luke Kenneth Casso... reversal of FXM mask for one-hot selection in OP_MTCR... tree | commitdiff
2020-08-30 Luke Kenneth Casso... working on dcache.py tree | commitdiff
2020-08-30 Luke Kenneth Casso... tidyup on mul proof tree | commitdiff
2020-08-30 Luke Kenneth Casso... set mul post_stage o.ok only when needed, and fix xer_s... tree | commitdiff
2020-08-30 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc tree | commitdiff
2020-08-30 Cole Poiriericache.py commit progress, about a third through the... tree | commitdiff
2020-08-29 Samuel A. Falvo IIQualify XER_OV output in proof tree | commitdiff
2020-08-29 Samuel A. Falvo IIFix test breakage in MUL proofs tree | commitdiff
2020-08-29 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc tree | commitdiff
2020-08-29 Cole Poiriermmu.py, dcache.py, mem_types.py change types capitaliza... tree | commitdiff
2020-08-29 Cole Poiriermem_types add more types from common.vhdl specifially... tree | commitdiff
2020-08-29 Cole Poiriermem_types.py arrange in alphabetical order for ease... tree | commitdiff
2020-08-29 Samuel A. Falvo IIBROKEN: xer_ov_o != dut.o.xer_ov.data ???!!! tree | commitdiff
2020-08-29 Cole Poiriermmu.py remove duplicate comment left over from mmu... tree | commitdiff
2020-08-29 Cole Poiriericache.py initial commit of first attempt at translatio... tree | commitdiff
2020-08-29 Cesar StraussMove new write_gtkw and its example to nmutil tree | commitdiff
2020-08-29 Luke Kenneth Casso... minor code-shuffle, comments tree | commitdiff
2020-08-29 Luke Kenneth Casso... slowly morphing towards using an XER bit-field selector... tree | commitdiff
2020-08-29 Samuel A. Falvo IIMUL pipeline formal proofs complete, I *think*. tree | commitdiff
2020-08-29 Luke Kenneth Casso... break down XER into flags tree | commitdiff
2020-08-29 Luke Kenneth Casso... add XER read via DMI interface to sim.py tree | commitdiff
2020-08-29 Luke Kenneth Casso... add hack to get at XER through DMI interface tree | commitdiff
2020-08-29 Samuel A. Falvo IIWIP: prep for 64-bit insns tree | commitdiff
2020-08-29 Luke Kenneth Casso... yep disable OE for MULH64/32 and EXTS and CNTZ tree | commitdiff
2020-08-29 Luke Kenneth Casso... investigating CR mtocrf / mfocrf tree | commitdiff
2020-08-29 Luke Kenneth Casso... add additional CR regression tests tree | commitdiff
2020-08-29 Luke Kenneth Casso... allow pseudocode numbering to decrement in for-loops tree | commitdiff
2020-08-29 Luke Kenneth Casso... add wat to write out raw binary assembled programs tree | commitdiff
2020-08-29 Luke Kenneth Casso... CR FXM becomes a full mask. tree | commitdiff
2020-08-28 Cole Poirierdcache.py add first attempt at translation of dcache_tb... tree | commitdiff
2020-08-27 Cole Poirierdcache.py add skeleton sim and test adapted from mmu... tree | commitdiff
2020-08-27 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc tree | commitdiff
2020-08-27 Cole Poirierdcache.py implement the remaining vhdl generate stateme... tree | commitdiff
2020-08-27 Luke Kenneth Casso... https://bugs.libre-soc.org/show_bug.cgi?id=476 tree | commitdiff
2020-08-27 Luke Kenneth Casso... xer so is not being passed through to CR0 tree | commitdiff
2020-08-27 Luke Kenneth Casso... really bad hack to fix simulator bug in carry handling tree | commitdiff
2020-08-27 Luke Kenneth Casso... augment addme test case to show bug #476 tree | commitdiff
2020-08-27 Luke Kenneth Casso... add addze and addme uni tests tree | commitdiff
2020-08-27 Luke Kenneth Casso... incompatibility with POWER9 on mulhw/u due to lack... tree | commitdiff
2020-08-27 Luke Kenneth Casso... overflow-enable does not occur on shift operations tree | commitdiff
2020-08-27 Luke Kenneth Casso... oink, write_cr shiftrot record width was zero (??) tree | commitdiff
2020-08-27 Luke Kenneth Casso... sorting out shift_rot to use new output stage data... tree | commitdiff
2020-08-27 Luke Kenneth Casso... need to read SO if Rc=1 tree | commitdiff
2020-08-27 Luke Kenneth Casso... reorg of SO handling related to CR0 tree | commitdiff
2020-08-26 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc tree | commitdiff
2020-08-26 Cole Poirierdcache.py replace subtypes/types/constant aliases with... tree | commitdiff
2020-08-26 Luke Kenneth Casso... use sub-test in logical test_pipe_caller tree | commitdiff
2020-08-26 Luke Kenneth Casso... investigating div fsm and simulator bug tree | commitdiff
2020-08-25 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc tree | commitdiff
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