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more rename of exception_o to exc_o, add convenience function in TestCore
[soc.git]
/
src
/
2021-04-23
Luke Kenneth Casso...
removing more as moved over to openpower-isa
tree
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commitdiff
2021-04-23
Luke Kenneth Casso...
submodule update
tree
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commitdiff
2021-04-22
Luke Kenneth Casso...
add debugging and buffering to CacheRam
tree
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commitdiff
2021-04-22
Luke Kenneth Casso...
whitespace
tree
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commitdiff
2021-04-22
Luke Kenneth Casso...
r1.end_row_ix off-by-one in dcache
tree
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commitdiff
2021-04-22
Luke Kenneth Casso...
sync missing in dcache
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commitdiff
2021-04-22
Luke Kenneth Casso...
dcache.py code-comments
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commitdiff
2021-04-22
Luke Kenneth Casso...
cleanup dcache
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commitdiff
2021-04-22
Luke Kenneth Casso...
error using sync, should have been comb
tree
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commitdiff
2021-04-22
Cesar Strauss
Implement CR predication
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commitdiff
2021-04-21
Cesar Strauss
CR sub-fields are stored in MSB0 order
tree
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commitdiff
2021-04-21
Luke Kenneth Casso...
experimenting with dcache
tree
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commitdiff
2021-04-21
Tobias Platen
testcase: pass PRTBL to mmu
tree
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commitdiff
2021-04-21
Cesar Strauss
Add CR predication test case for TestIssuer
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commitdiff
2021-04-21
Cesar Strauss
Fix comment in CR predication test case
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commitdiff
2021-04-21
Cesar Strauss
Fix sense of "invert" signal
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commitdiff
2021-04-20
Luke Kenneth Casso...
add enable MMU option to issuer_verilog.py
tree
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commitdiff
2021-04-20
Luke Kenneth Casso...
cannot pass in arguments to Core - must be done with...
tree
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commitdiff
2021-04-20
Luke Kenneth Casso...
use soc.bus.sram instead of nmigen_soc.wishbone.sram
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commitdiff
2021-04-20
Luke Kenneth Casso...
add wishbone sram.py (move from nmigen-soc)
tree
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commitdiff
2021-04-19
Luke Kenneth Casso...
give independent names to spblock512w64b8ws
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commitdiff
2021-04-18
Luke Kenneth Casso...
give spblock512 a name as a submodule
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commitdiff
2021-04-18
Luke Kenneth Casso...
create signal on test_issuer which gives PLL clk_sel_i...
tree
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commitdiff
2021-04-18
Luke Kenneth Casso...
rename SPBlock_512W64B8W to lowercase
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commitdiff
2021-04-18
Luke Kenneth Casso...
submodule update
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commitdiff
2021-04-18
Luke Kenneth Casso...
rename PLL pins to match LIP6.fr PLL
tree
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commitdiff
2021-04-18
Luke Kenneth Casso...
core_stopped_i unused: remove
tree
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commitdiff
2021-04-18
Luke Kenneth Casso...
submodule update
tree
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commitdiff
2021-04-18
Luke Kenneth Casso...
submodule update
tree
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commitdiff
2021-04-17
Luke Kenneth Casso...
experiment with alternative PID in radix mmu
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commitdiff
2021-04-17
Luke Kenneth Casso...
pass in SPRs each time on radix test
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commitdiff
2021-04-17
Luke Kenneth Casso...
add LD/ST radix unit test
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commitdiff
2021-04-17
Cesar Strauss
Implement 1<<r3 directly by a shift
tree
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commitdiff
2021-04-17
Tobias Platen
radixmmu: fix my mistake about pgbase size
tree
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commitdiff
2021-04-16
Luke Kenneth Casso...
submodule update
tree
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commitdiff
2021-04-16
Luke Kenneth Casso...
jtag utils, send tms before tck
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commitdiff
2021-04-16
Tobias Platen
pass the "old" value of shift to _new_lookup
tree
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commitdiff
2021-04-16
Luke Kenneth Casso...
sigh, new_shift wrong bitwidth
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commitdiff
2021-04-16
Luke Kenneth Casso...
put mbits back into segment_check (like it is in microwatt)
tree
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commitdiff
2021-04-16
Luke Kenneth Casso...
radixmmu cleanup
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commitdiff
2021-04-16
Luke Kenneth Casso...
call addrshift and get_pgtable_addr inside while loop...
tree
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commitdiff
2021-04-16
Luke Kenneth Casso...
code-cleanup in radixmmu
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commitdiff
2021-04-15
Luke Kenneth Casso...
whitespace and corrections to NLS, RTS1, RTS2
tree
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commitdiff
2021-04-15
Tobias Platen
fix radix testcase
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commitdiff
2021-04-15
Luke Kenneth Casso...
concat en_sigs together in JTAG to make sure they are...
tree
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commitdiff
2021-04-15
Luke Kenneth Casso...
add icachemmu option to ISACaller
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commitdiff
2021-04-14
Luke Kenneth Casso...
submodule update
tree
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commitdiff
2021-04-14
Luke Kenneth Casso...
whitespace
tree
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commitdiff
2021-04-14
Luke Kenneth Casso...
submodule update
tree
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commitdiff
2021-04-14
Tobias Platen
update test_caller_radix.py
tree
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commitdiff
2021-04-14
Tobias Platen
radixmmu: handle badtree
tree
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commitdiff
2021-04-14
Tobias Platen
update test case for radix mmu
tree
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commitdiff
2021-04-14
Tobias Platen
radixmmu: error handling
tree
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commitdiff
2021-04-13
Tobias Platen
more fixes for radixmmu.py
tree
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commitdiff
2021-04-13
Tobias Platen
fix AttributeError in radixmmu testcase
tree
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commitdiff
2021-04-12
Tobias Platen
radixmmu.py: cleanup
tree
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commitdiff
2021-04-11
Tobias Platen
fix bug in radixmmu.py
tree
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commitdiff
2021-04-11
Tobias Platen
radixmmu: more work on segment check
tree
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commitdiff
2021-04-10
Cesar Strauss
Implement 1<<r3 predicate mode
tree
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commitdiff
2021-04-10
Cesar Strauss
Add 1<<r3 test cases to TestIssuer
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commitdiff
2021-04-10
Cesar Strauss
Add test cases for 1<<r3 predication
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commitdiff
2021-04-09
Luke Kenneth Casso...
add blinken lights assembly (not used yet)
tree
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commitdiff
2021-04-09
Luke Kenneth Casso...
test firmware upload program needed to branch back...
tree
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commitdiff
2021-04-08
Luke Kenneth Casso...
sort out pc reset when DMI interface requests reset
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commitdiff
2021-04-08
Luke Kenneth Casso...
submodule update
tree
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commitdiff
2021-04-08
Luke Kenneth Casso...
argh, wb jtag stall probably is not working
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commitdiff
2021-04-08
Luke Kenneth Casso...
upload over 32-bit JTAG Wishbone
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commitdiff
2021-04-08
Luke Kenneth Casso...
shrink JTAG master bus to 32-bit (match with litex)
tree
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commitdiff
2021-04-07
Luke Kenneth Casso...
submodule update
tree
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commitdiff
2021-04-07
Tobias Platen
WIP: calculate address of first page table entry
tree
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commitdiff
2021-04-07
Tobias Platen
radixmmu: fix segment_check function and its caller
tree
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commitdiff
2021-04-06
Luke Kenneth Casso...
4k SRAM Instance needs write-enable @ 8-bit width
tree
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commitdiff
2021-04-06
Luke Kenneth Casso...
8-bit granularity on JTAG wishbone
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commitdiff
2021-04-06
Luke Kenneth Casso...
remove unneeded code
tree
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commitdiff
2021-04-06
Staf Verhaegen
soc-cocotb-sim submodule update
tree
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commitdiff
2021-04-06
Tobias Platen
add mmu_states.dia
tree
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commitdiff
2021-04-06
Luke Kenneth Casso...
git submodule update
tree
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commitdiff
2021-04-06
Cesar Strauss
Make the VL loop reentrant in HDL
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commitdiff
2021-04-06
Cesar Strauss
Add a HDL test case, where we start at the middle of...
tree
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commitdiff
2021-04-06
Cesar Strauss
Start the test case from a point where the predicate...
tree
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commitdiff
2021-04-05
Luke Kenneth Casso...
litex submodule update
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commitdiff
2021-04-05
Luke Kenneth Casso...
submodule update
tree
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commitdiff
2021-04-04
Staf Verhaegen
soc-cocotb-sim submodule update
tree
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commitdiff
2021-04-04
Cesar Strauss
Add test case for reentrant VL loop
tree
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commitdiff
2021-04-03
Cesar Strauss
Reminder for a possible hardware optimization
tree
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commitdiff
2021-04-03
Cesar Strauss
Be more precise when using a one-bit constant
tree
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commitdiff
2021-04-03
Cesar Strauss
Fix typo
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commitdiff
2021-04-03
Cesar Strauss
Add test case with all mask bits equal to zero
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commitdiff
2021-04-03
Cesar Strauss
Add a test case for integer single predication
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commitdiff
2021-04-03
Cesar Strauss
Disallow unknown encmodes in SVP64 Assembly
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commitdiff
2021-04-03
Cesar Strauss
Enable remaining disabled test cases
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commitdiff
2021-04-03
Cesar Strauss
Allow the Simulator to handle back-to-back signaling...
tree
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commitdiff
2021-04-03
Cesar Strauss
Signal the simulator when completing a VL loop
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commitdiff
2021-04-03
Cesar Strauss
Fix typo
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commitdiff
2021-04-03
Cesar Strauss
Add twin predication test
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commitdiff
2021-04-02
Cesar Strauss
End VL loop as soon as either src/dst step reaches VL
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commitdiff
2021-04-02
Cesar Strauss
Fix typo
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commitdiff
2021-04-02
Cesar Strauss
Add VEXPAND test case for the ISA Simulator
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commitdiff
2021-04-02
Cesar Strauss
Add VCOMPRESS test case for the ISA Simulator
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commitdiff
2021-04-02
Cesar Strauss
Put sanity check inside the existing '2Pred' case,...
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commitdiff
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