soc.git
3 years agoupload over 32-bit JTAG Wishbone
Luke Kenneth Casson Leighton [Thu, 8 Apr 2021 20:38:55 +0000 (21:38 +0100)]
upload over 32-bit JTAG Wishbone

3 years agoshrink JTAG master bus to 32-bit (match with litex)
Luke Kenneth Casson Leighton [Thu, 8 Apr 2021 20:21:09 +0000 (21:21 +0100)]
shrink JTAG master bus to 32-bit (match with litex)

3 years agosubmodule update
Luke Kenneth Casson Leighton [Wed, 7 Apr 2021 19:27:37 +0000 (20:27 +0100)]
submodule update

3 years agoWIP: calculate address of first page table entry
Tobias Platen [Wed, 7 Apr 2021 19:17:35 +0000 (21:17 +0200)]
WIP: calculate address of first page table entry

3 years agoradixmmu: fix segment_check function and its caller
Tobias Platen [Wed, 7 Apr 2021 18:26:54 +0000 (20:26 +0200)]
radixmmu: fix segment_check function and its caller

3 years ago4k SRAM Instance needs write-enable @ 8-bit width
Luke Kenneth Casson Leighton [Tue, 6 Apr 2021 21:07:12 +0000 (22:07 +0100)]
4k SRAM Instance needs write-enable @ 8-bit width

3 years ago8-bit granularity on JTAG wishbone
Luke Kenneth Casson Leighton [Tue, 6 Apr 2021 20:38:04 +0000 (21:38 +0100)]
8-bit granularity on JTAG wishbone

3 years agoremove unneeded code
Luke Kenneth Casson Leighton [Tue, 6 Apr 2021 20:35:12 +0000 (21:35 +0100)]
remove unneeded code

3 years agosoc-cocotb-sim submodule update
Staf Verhaegen [Tue, 6 Apr 2021 18:50:58 +0000 (20:50 +0200)]
soc-cocotb-sim submodule update

3 years agoadd mmu_states.dia
Tobias Platen [Tue, 6 Apr 2021 17:21:14 +0000 (19:21 +0200)]
add mmu_states.dia

3 years agogit submodule update
Luke Kenneth Casson Leighton [Tue, 6 Apr 2021 14:58:36 +0000 (15:58 +0100)]
git submodule update

3 years agoMake the VL loop reentrant in HDL
Cesar Strauss [Tue, 6 Apr 2021 11:31:14 +0000 (08:31 -0300)]
Make the VL loop reentrant in HDL

This is done by shifting-out already used mask bits, at predicate fetch.
The corresponding test case now passes.

3 years agoAdd a HDL test case, where we start at the middle of the VL loop
Cesar Strauss [Tue, 6 Apr 2021 11:26:43 +0000 (08:26 -0300)]
Add a HDL test case, where we start at the middle of the VL loop

It is expected to fail, since the HDL is not reentrant at this moment.

3 years agoStart the test case from a point where the predicate bits are zeros
Cesar Strauss [Tue, 6 Apr 2021 11:18:26 +0000 (08:18 -0300)]
Start the test case from a point where the predicate bits are zeros

Since SVSTATE is user-programmable, src/dst step can really point anywhere,
at instruction start. Although interrupts will always restore src/dest step
pointing to a set mask bit, this is not guaranteed in general.

3 years agolitex submodule update
Luke Kenneth Casson Leighton [Mon, 5 Apr 2021 11:06:31 +0000 (12:06 +0100)]
litex submodule update

3 years agosubmodule update
Luke Kenneth Casson Leighton [Mon, 5 Apr 2021 10:47:10 +0000 (11:47 +0100)]
submodule update

3 years agosoc-cocotb-sim submodule update
Staf Verhaegen [Sun, 4 Apr 2021 16:09:17 +0000 (18:09 +0200)]
soc-cocotb-sim submodule update

3 years agoAdd test case for reentrant VL loop
Cesar Strauss [Sun, 4 Apr 2021 11:59:22 +0000 (08:59 -0300)]
Add test case for reentrant VL loop

We explicitly initialize src/dst step, as if we were returning from an
interrupt.

3 years agoReminder for a possible hardware optimization
Cesar Strauss [Sat, 3 Apr 2021 20:12:30 +0000 (17:12 -0300)]
Reminder for a possible hardware optimization

3 years agoBe more precise when using a one-bit constant
Cesar Strauss [Sat, 3 Apr 2021 20:02:39 +0000 (17:02 -0300)]
Be more precise when using a one-bit constant

3 years agoFix typo
Cesar Strauss [Sat, 3 Apr 2021 19:18:56 +0000 (16:18 -0300)]
Fix typo

3 years agoAdd test case with all mask bits equal to zero
Cesar Strauss [Sat, 3 Apr 2021 19:16:48 +0000 (16:16 -0300)]
Add test case with all mask bits equal to zero

3 years agoAdd a test case for integer single predication
Cesar Strauss [Sat, 3 Apr 2021 19:04:49 +0000 (16:04 -0300)]
Add a test case for integer single predication

3 years agoDisallow unknown encmodes in SVP64 Assembly
Cesar Strauss [Sat, 3 Apr 2021 18:48:50 +0000 (15:48 -0300)]
Disallow unknown encmodes in SVP64 Assembly

3 years agoEnable remaining disabled test cases
Cesar Strauss [Sat, 3 Apr 2021 18:45:39 +0000 (15:45 -0300)]
Enable remaining disabled test cases

They all work, now, after the ISA Caller fixes.

3 years agoAllow the Simulator to handle back-to-back signaling from TestIssuer
Cesar Strauss [Sat, 3 Apr 2021 18:40:31 +0000 (15:40 -0300)]
Allow the Simulator to handle back-to-back signaling from TestIssuer

TestIssuer can signal the end of an instruction and, after skipping mask
bits, signal the end of the VL loop, right on the following cycle.
Since there is no handshake between TestIssuer and Simulator, we need to
remove any wait state that would cause the Simulator to miss the one-clock
pulse.

3 years agoSignal the simulator when completing a VL loop
Cesar Strauss [Sat, 3 Apr 2021 18:21:37 +0000 (15:21 -0300)]
Signal the simulator when completing a VL loop

When we reach the end of the VL loop, by skipping masked bits in the
predicate, we still need to synchronize with the Simulator, even if no
instruction was issued.

3 years agoFix typo
Cesar Strauss [Sat, 3 Apr 2021 11:21:21 +0000 (08:21 -0300)]
Fix typo

3 years agoAdd twin predication test
Cesar Strauss [Sat, 3 Apr 2021 11:07:51 +0000 (08:07 -0300)]
Add twin predication test

Another simulator failure. Seems like the VL loop is still not terminating
properly. Will investigate.

3 years agoEnd VL loop as soon as either src/dst step reaches VL
Cesar Strauss [Fri, 2 Apr 2021 22:26:21 +0000 (19:26 -0300)]
End VL loop as soon as either src/dst step reaches VL

Also, avoid incrementing dststep beyond VL-1

3 years agoFix typo
Cesar Strauss [Fri, 2 Apr 2021 22:20:26 +0000 (19:20 -0300)]
Fix typo

3 years agoAdd VEXPAND test case for the ISA Simulator
Cesar Strauss [Fri, 2 Apr 2021 20:43:15 +0000 (17:43 -0300)]
Add VEXPAND test case for the ISA Simulator

The test currently does not pass, there must be a bug somewhere.
Seems like it is skipping the middle source element, as if it was doing
single-pred.

3 years agoAdd VCOMPRESS test case for the ISA Simulator
Cesar Strauss [Fri, 2 Apr 2021 20:25:13 +0000 (17:25 -0300)]
Add VCOMPRESS test case for the ISA Simulator

3 years agoPut sanity check inside the existing '2Pred' case, and simplify
Cesar Strauss [Fri, 2 Apr 2021 19:58:48 +0000 (16:58 -0300)]
Put sanity check inside the existing '2Pred' case, and simplify

3 years agoEnforce explicit src/dest masks on CR twin-predication
Cesar Strauss [Fri, 2 Apr 2021 19:53:32 +0000 (16:53 -0300)]
Enforce explicit src/dest masks on CR twin-predication

3 years agoDisallow mixing of sm=xx and/or dm=xx with m=xx on twin-pred
Cesar Strauss [Fri, 2 Apr 2021 19:32:33 +0000 (16:32 -0300)]
Disallow mixing of sm=xx and/or dm=xx with m=xx on twin-pred

3 years agoDisallow dm=xx on single predication
Cesar Strauss [Fri, 2 Apr 2021 18:51:46 +0000 (15:51 -0300)]
Disallow dm=xx on single predication

Adjust test cases accordingly.

3 years agoFix typo
Cesar Strauss [Fri, 2 Apr 2021 17:04:20 +0000 (14:04 -0300)]
Fix typo

3 years agoReally enforce sm=xx not being allowed on single-pred
Cesar Strauss [Fri, 2 Apr 2021 15:06:00 +0000 (12:06 -0300)]
Really enforce sm=xx not being allowed on single-pred

Before, using m=xx together with sm=xx would defeat the assertion.

3 years agoKeep mask mode flags separate
Cesar Strauss [Fri, 2 Apr 2021 14:23:31 +0000 (11:23 -0300)]
Keep mask mode flags separate

Before, when m=xx was seen, we couldn't tell whether sm=xx or dm=xx was
also seen. We will need this, later.
Adjust uses accordingly, preserving truth value.

3 years agogit submodule update
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 22:41:24 +0000 (23:41 +0100)]
git submodule update

3 years agoTWI enabled in JTAG boundary scan
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 22:14:58 +0000 (23:14 +0100)]
TWI enabled in JTAG boundary scan

3 years agogit submodule update
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 22:08:10 +0000 (23:08 +0100)]
git submodule update

3 years agoreduce subset of functions to be created in JTAG boundary scan
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 22:07:53 +0000 (23:07 +0100)]
reduce subset of functions to be created in JTAG boundary scan

3 years agouse OrderedDict to restore exact order from JSON file
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 22:07:26 +0000 (23:07 +0100)]
use OrderedDict to restore exact order from JSON file

3 years agoadd soc-cocotb-sim submodule
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 21:46:40 +0000 (22:46 +0100)]
add soc-cocotb-sim submodule

3 years agosubmodule update
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 15:52:11 +0000 (16:52 +0100)]
submodule update

3 years agolibresoc-litex submodule update
Staf Verhaegen [Thu, 1 Apr 2021 12:56:53 +0000 (14:56 +0200)]
libresoc-litex submodule update

3 years agobug in iverilog, segfaults due to empty case statement
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 12:17:53 +0000 (13:17 +0100)]
bug in iverilog, segfaults due to empty case statement

3 years agoadd no pll ls180 build
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 12:10:00 +0000 (13:10 +0100)]
add no pll ls180 build

3 years agolibresoc-litex submodule update
Staf Verhaegen [Thu, 1 Apr 2021 11:51:33 +0000 (13:51 +0200)]
libresoc-litex submodule update

3 years ago_new_lookup: remove unused argument mbits
Tobias Platen [Wed, 31 Mar 2021 19:45:57 +0000 (21:45 +0200)]
_new_lookup: remove unused argument mbits

3 years agoradixmmu: read prtable entry
Tobias Platen [Wed, 31 Mar 2021 18:42:24 +0000 (20:42 +0200)]
radixmmu: read prtable entry

3 years agoradixmmu.py: remove redunant code
Tobias Platen [Wed, 31 Mar 2021 17:35:14 +0000 (19:35 +0200)]
radixmmu.py: remove redunant code

3 years agosubmodule update
Luke Kenneth Casson Leighton [Wed, 31 Mar 2021 13:41:48 +0000 (14:41 +0100)]
submodule update

3 years agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Tue, 30 Mar 2021 19:28:16 +0000 (21:28 +0200)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

3 years agomore work on _prtable_lookup and testcase
Tobias Platen [Tue, 30 Mar 2021 19:27:23 +0000 (21:27 +0200)]
more work on _prtable_lookup and testcase

3 years agoadd comments
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 19:16:12 +0000 (20:16 +0100)]
add comments

3 years agouse PRTBL SPR in RADIXMMU
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 19:09:34 +0000 (20:09 +0100)]
use PRTBL SPR in RADIXMMU

3 years agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Tue, 30 Mar 2021 18:45:52 +0000 (20:45 +0200)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

3 years agocomment about microwatt implementation details
Tobias Platen [Tue, 30 Mar 2021 18:11:00 +0000 (20:11 +0200)]
comment about microwatt implementation details

3 years agosubmodule update
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 18:10:37 +0000 (19:10 +0100)]
submodule update

3 years agoadd comments, correct load addresses
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 17:40:32 +0000 (18:40 +0100)]
add comments, correct load addresses

3 years agoMerge branch 'master' of git.libre-soc.org:soc
Alain D D Williams [Tue, 30 Mar 2021 18:10:09 +0000 (19:10 +0100)]
Merge branch 'master' of git.libre-soc.org:soc

3 years agoAllow comments
Alain D D Williams [Tue, 30 Mar 2021 18:09:41 +0000 (19:09 +0100)]
Allow comments

3 years agoadd function _prtable_lookup and unit test
Tobias Platen [Tue, 30 Mar 2021 17:26:41 +0000 (19:26 +0200)]
add function _prtable_lookup and unit test

3 years agosubmodule update
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 16:52:44 +0000 (17:52 +0100)]
submodule update

3 years agomight have RADIXMMU at least semi-working... maybe
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 15:13:18 +0000 (16:13 +0100)]
might have RADIXMMU at least semi-working... maybe

3 years agouse assertEqual in RADIXMMU unit test
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 14:04:23 +0000 (15:04 +0100)]
use assertEqual in RADIXMMU unit test

3 years agoskip 1-pred check if m= used in SVP64Asm
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 13:20:27 +0000 (14:20 +0100)]
skip 1-pred check if m= used in SVP64Asm

3 years agoEnable VCOMPRESS test case
Cesar Strauss [Tue, 30 Mar 2021 12:47:56 +0000 (09:47 -0300)]
Enable VCOMPRESS test case

VEXPAND seems to have some issue in the Simulator maybe.

3 years agosubmodule update
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 12:35:14 +0000 (13:35 +0100)]
submodule update

3 years agoAdd new twin predication case
Cesar Strauss [Tue, 30 Mar 2021 12:27:11 +0000 (09:27 -0300)]
Add new twin predication case

Equivalent to VCOMPRESS followed by VEXPAND.

3 years agoAdjust twin predication cases for the new syntax
Cesar Strauss [Tue, 30 Mar 2021 12:22:25 +0000 (09:22 -0300)]
Adjust twin predication cases for the new syntax

3 years agoSkip leading zero bits on predicate masks
Cesar Strauss [Tue, 30 Mar 2021 11:57:48 +0000 (08:57 -0300)]
Skip leading zero bits on predicate masks

The PRED_SKIP state moves src/dst step to the next non-zero bit on the
mask.
The leading zeros on the mask (plus the set bit) are shifted out, while
the shifted amount is added to the step.
If the new step value would increase past VL, the loop is ended.

3 years agouse port name for INT regfile to match up with test_runner gtkw
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 11:34:40 +0000 (12:34 +0100)]
use port name for INT regfile to match up with test_runner gtkw

3 years agocorrections to Makefile for building / not-building 4k sram ls180
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 11:29:56 +0000 (12:29 +0100)]
corrections to Makefile for building / not-building 4k sram ls180

3 years agoMemory port seems to have been renamed
Cesar Strauss [Tue, 30 Mar 2021 11:21:09 +0000 (08:21 -0300)]
Memory port seems to have been renamed

3 years agobit of munging of Makefile, new targets
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 10:38:44 +0000 (11:38 +0100)]
bit of munging of Makefile, new targets

3 years agowhoops Makefile error
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 10:22:17 +0000 (11:22 +0100)]
whoops Makefile error

3 years agocorrect segment check (off by one in LE/BE convert
Luke Kenneth Casson Leighton [Mon, 29 Mar 2021 19:05:11 +0000 (20:05 +0100)]
correct segment check (off by one in LE/BE convert

3 years agoupdate submodule
Luke Kenneth Casson Leighton [Mon, 29 Mar 2021 18:18:44 +0000 (19:18 +0100)]
update submodule

3 years agosort out pywriter.py when run with no args
Luke Kenneth Casson Leighton [Mon, 29 Mar 2021 18:18:33 +0000 (19:18 +0100)]
sort out pywriter.py when run with no args

3 years agoremove "install" from run_sim dependency in Makefile
Luke Kenneth Casson Leighton [Mon, 29 Mar 2021 17:31:11 +0000 (18:31 +0100)]
remove "install" from run_sim dependency in Makefile

3 years agosvp64-enable passed through to PowerDecoderSubsets in core.py
Luke Kenneth Casson Leighton [Sun, 28 Mar 2021 22:57:45 +0000 (23:57 +0100)]
svp64-enable passed through to PowerDecoderSubsets in core.py

3 years agowhoops spelling mistake in SPRreduced Enums
Luke Kenneth Casson Leighton [Sun, 28 Mar 2021 22:56:36 +0000 (23:56 +0100)]
whoops spelling mistake in SPRreduced Enums

3 years agoMove DECODE_SV to its place between MASK_WAIT and INSN_EXECUTE
Cesar Strauss [Sun, 28 Mar 2021 18:18:28 +0000 (15:18 -0300)]
Move DECODE_SV to its place between MASK_WAIT and INSN_EXECUTE

3 years agoMove instruction decoding to after predication
Cesar Strauss [Sun, 28 Mar 2021 18:03:24 +0000 (15:03 -0300)]
Move instruction decoding to after predication

Since predication can update SRCSTEP and DESTSTEP, leave decoding for
after their final values are known.
So, "DECODE_SV" is now responsible for decoding, and sits in line between
"MASK_WAIT" and "INSN_EXECUTE".

3 years agoPrepare to advance src/dst step after getting the predicate mask
Cesar Strauss [Sun, 28 Mar 2021 16:57:36 +0000 (13:57 -0300)]
Prepare to advance src/dst step after getting the predicate mask

3 years agorather invasive reduction of SPR regfile size
Luke Kenneth Casson Leighton [Sun, 28 Mar 2021 15:48:53 +0000 (16:48 +0100)]
rather invasive reduction of SPR regfile size
done by dynamically creating an alternative SPR Enum

3 years agoadd option to reduce number of regfile ports (get DFFs down in ls180)
Luke Kenneth Casson Leighton [Sun, 28 Mar 2021 13:53:20 +0000 (14:53 +0100)]
add option to reduce number of regfile ports (get DFFs down in ls180)

3 years agoreduce number of regfile ports
Luke Kenneth Casson Leighton [Sun, 28 Mar 2021 13:37:16 +0000 (14:37 +0100)]
reduce number of regfile ports

3 years agoreduce regfile port usage on non-svp64
Luke Kenneth Casson Leighton [Sun, 28 Mar 2021 13:29:37 +0000 (14:29 +0100)]
reduce regfile port usage on non-svp64

3 years agoradixmmu.py: cleanup, documentation
Tobias Platen [Thu, 25 Mar 2021 19:33:22 +0000 (20:33 +0100)]
radixmmu.py: cleanup, documentation

3 years agofix _get_prtable_addr, cleanup
Tobias Platen [Thu, 25 Mar 2021 19:24:49 +0000 (20:24 +0100)]
fix _get_prtable_addr, cleanup

3 years agocomment about using PriorityEncoder
Luke Kenneth Casson Leighton [Wed, 24 Mar 2021 18:59:42 +0000 (18:59 +0000)]
comment about using PriorityEncoder

3 years agodebug output
Luke Kenneth Casson Leighton [Wed, 24 Mar 2021 17:11:00 +0000 (17:11 +0000)]
debug output

3 years agoadd comment skipping in pagereader.py
Luke Kenneth Casson Leighton [Wed, 24 Mar 2021 17:06:29 +0000 (17:06 +0000)]
add comment skipping in pagereader.py

3 years agomake svp64 isa caller unit tests more obvious
Luke Kenneth Casson Leighton [Wed, 24 Mar 2021 16:10:00 +0000 (16:10 +0000)]
make svp64 isa caller unit tests more obvious

3 years agoadd option to stop writing isa all.py in pseudocode directory
Luke Kenneth Casson Leighton [Wed, 24 Mar 2021 15:44:39 +0000 (15:44 +0000)]
add option to stop writing isa all.py in pseudocode directory