Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 12:50:31 +0000 (13:50 +0100)]
add comment headings with spec page numbers
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 12:45:58 +0000 (13:45 +0100)]
comment on op.insn ordering
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 12:42:53 +0000 (13:42 +0100)]
code-shuffle, add comments
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 11:59:13 +0000 (12:59 +0100)]
add TT.size and use it in PowerDecoder and trap input record
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 11:57:24 +0000 (12:57 +0100)]
inline comments in trap proof
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 11:54:56 +0000 (12:54 +0100)]
note that traptype MUST increase in bitwidth corresponding to additions
to TT
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 10:41:44 +0000 (11:41 +0100)]
fix branch main_stage proof, add ctr 32-bit, fix BCREG
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 10:14:32 +0000 (11:14 +0100)]
rework branch proof to use br_input_record
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 09:50:47 +0000 (10:50 +0100)]
update README for pipe_data.py
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 09:29:58 +0000 (10:29 +0100)]
reduce number of FastRegs read ports
Luke Kenneth Casson Leighton [Wed, 22 Jul 2020 09:29:36 +0000 (10:29 +0100)]
comments on what goes into CommonPipeSpec
Samuel A. Falvo II [Wed, 22 Jul 2020 06:03:34 +0000 (23:03 -0700)]
Complete FV properties for OP_TRAP instructions.
Samuel A. Falvo II [Wed, 22 Jul 2020 03:08:32 +0000 (20:08 -0700)]
PEP8 compliance
Jacob Lifshay [Wed, 22 Jul 2020 02:03:56 +0000 (19:03 -0700)]
working on FSMDivCoreStage
Jacob Lifshay [Wed, 22 Jul 2020 01:16:37 +0000 (18:16 -0700)]
fix test_div_state_fsm
Samuel A. Falvo II [Tue, 21 Jul 2020 21:45:59 +0000 (14:45 -0700)]
Completed SC FV properties
Samuel A. Falvo II [Tue, 21 Jul 2020 21:16:34 +0000 (14:16 -0700)]
Refine properties to comply with spec
Samuel A. Falvo II [Tue, 21 Jul 2020 19:16:09 +0000 (12:16 -0700)]
Fix where msr_i gets its value from
Samuel A. Falvo II [Tue, 21 Jul 2020 19:00:22 +0000 (12:00 -0700)]
Merge in recent updates to TRAP FV properties.
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 18:36:39 +0000 (19:36 +0100)]
convert branch pipeline to use msr/cia as immediates
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 18:36:09 +0000 (19:36 +0100)]
put set_msr and set_cia back in for now
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 18:35:39 +0000 (19:35 +0100)]
interesting bug in test_compunit.py when there are no operands
rdmask, if left set, interferes with the next instruction, but
only when there are no operands
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 17:49:10 +0000 (18:49 +0100)]
testing if MultiCompUnit can handle no input regs (it can)
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 17:39:52 +0000 (18:39 +0100)]
disable cxxsim for now
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 14:25:27 +0000 (15:25 +0100)]
move cia and msr to trap input record
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 14:23:04 +0000 (15:23 +0100)]
set ISACaller.msr rather than namespace[MSR]
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 14:22:28 +0000 (15:22 +0100)]
when running an exception (trap) after "reset" must copy msr/cia state
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 14:14:00 +0000 (15:14 +0100)]
spurious imports of FHDLTestCase, should be from nmutil
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 13:30:47 +0000 (14:30 +0100)]
whitespace
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 13:24:30 +0000 (14:24 +0100)]
add PC (CIA) to PowerDecode2 "state" for passing into input records
see https://bugs.libre-soc.org/show_bug.cgi?id=435
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 13:10:54 +0000 (14:10 +0100)]
add msr exception bits setting function in hardware
and do same thing in ISACaller trap
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 12:53:28 +0000 (13:53 +0100)]
make cxxsim optional and print warning
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 09:50:37 +0000 (10:50 +0100)]
corrections to trap proof see
https://bugs.libre-soc.org/show_bug.cgi?id=421#c17 and
https://bugs.libre-soc.org/show_bug.cgi?id=421#c18
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 09:45:33 +0000 (10:45 +0100)]
use alias for msr_i in trap proof
Luke Kenneth Casson Leighton [Tue, 21 Jul 2020 09:41:36 +0000 (10:41 +0100)]
correct trap spec page interrupt ref
Samuel A. Falvo II [Mon, 20 Jul 2020 23:17:00 +0000 (16:17 -0700)]
Rework SC properties to conform to style
Samuel A. Falvo II [Mon, 20 Jul 2020 23:08:50 +0000 (16:08 -0700)]
Formal properties for RFID.
Cesar Strauss [Mon, 20 Jul 2020 22:00:59 +0000 (19:00 -0300)]
Document the move of sdir from data_i to op.
Also, give op.sdir a name based on "op", to distinguish it
from internal signals.
Cesar Strauss [Mon, 20 Jul 2020 20:13:27 +0000 (17:13 -0300)]
Remove extra yield from test case.
Seems pysim is correct, after all. There seems to be some
strange interaction between cxxrtl and python.
Luke Kenneth Casson Leighton [Sun, 19 Jul 2020 19:58:00 +0000 (20:58 +0100)]
do not start core in terminated mode
Luke Kenneth Casson Leighton [Sun, 19 Jul 2020 19:55:10 +0000 (20:55 +0100)]
explicitly set up a pc_i_ok signal in test_microwatt.py
Luke Kenneth Casson Leighton [Sun, 19 Jul 2020 19:51:40 +0000 (20:51 +0100)]
expose core_stop_i to outside as well
Luke Kenneth Casson Leighton [Sun, 19 Jul 2020 19:45:17 +0000 (20:45 +0100)]
set go_insn_i to non-resetless
Luke Kenneth Casson Leighton [Sun, 19 Jul 2020 19:44:18 +0000 (20:44 +0100)]
add issuer verilog generator
Luke Kenneth Casson Leighton [Sun, 19 Jul 2020 19:39:35 +0000 (20:39 +0100)]
update to expose signals at top-level of issuer
Luke Kenneth Casson Leighton [Sun, 19 Jul 2020 15:06:35 +0000 (16:06 +0100)]
convert compalu multi test to Simulator() (was run_simulation)
Luke Kenneth Casson Leighton [Sun, 19 Jul 2020 15:06:28 +0000 (16:06 +0100)]
convert compalu multi test to Simulator() (was run_simulation)
Luke Kenneth Casson Leighton [Sun, 19 Jul 2020 14:55:50 +0000 (15:55 +0100)]
use same write_vcd for cxxsim as pysim
Luke Kenneth Casson Leighton [Sun, 19 Jul 2020 14:53:36 +0000 (15:53 +0100)]
fix bug in alu_fsm.py found by cxxsim: missing one cycle hold of ready_i
Luke Kenneth Casson Leighton [Sun, 19 Jul 2020 11:32:20 +0000 (12:32 +0100)]
add some CompUnit demo tests of the alu_fsm example
Luke Kenneth Casson Leighton [Sun, 19 Jul 2020 11:31:56 +0000 (12:31 +0100)]
move sdir to CompFSMOpSubset in alu_fsm example
Luke Kenneth Casson Leighton [Sun, 19 Jul 2020 11:12:27 +0000 (12:12 +0100)]
add CompFSMOpSubset, also change dir to sdir
(dir is a python keyword, gets highlighted in editors)
Luke Kenneth Casson Leighton [Sun, 19 Jul 2020 11:10:11 +0000 (12:10 +0100)]
remove unneeded import
Luke Kenneth Casson Leighton [Sun, 19 Jul 2020 10:59:32 +0000 (11:59 +0100)]
if nmigen.sim.pysim import fails use nmigen.back.pysim
Luke Kenneth Casson Leighton [Sun, 19 Jul 2020 10:59:05 +0000 (11:59 +0100)]
use iocontrol PrevControl / NextControl instead of dummy classes
Luke Kenneth Casson Leighton [Sun, 19 Jul 2020 10:49:20 +0000 (11:49 +0100)]
add DivTestCase to test_issuer.py (commented out for now)
Cesar Strauss [Sun, 19 Jul 2020 00:39:32 +0000 (21:39 -0300)]
Implement control path and unit test.
Luke Kenneth Casson Leighton [Sat, 18 Jul 2020 22:17:45 +0000 (23:17 +0100)]
worked out that DivPipeSpec can be given a default. gets DivFunctionUnit
working again
Luke Kenneth Casson Leighton [Sat, 18 Jul 2020 14:05:05 +0000 (15:05 +0100)]
missing conversion of DIV to Div
Luke Kenneth Casson Leighton [Sat, 18 Jul 2020 14:04:43 +0000 (15:04 +0100)]
add option to generate verilog
Luke Kenneth Casson Leighton [Sat, 18 Jul 2020 14:03:31 +0000 (15:03 +0100)]
whoops use slice not range
Luke Kenneth Casson Leighton [Sat, 18 Jul 2020 13:58:30 +0000 (14:58 +0100)]
syntax error
Cesar Strauss [Sat, 18 Jul 2020 19:02:19 +0000 (16:02 -0300)]
Implement the Shifter data path
Cesar Strauss [Sat, 18 Jul 2020 13:52:06 +0000 (10:52 -0300)]
Document move of the next port data
Luke Kenneth Casson Leighton [Sat, 18 Jul 2020 12:09:14 +0000 (13:09 +0100)]
add SR latch cxxrtl backend demo
Luke Kenneth Casson Leighton [Sat, 18 Jul 2020 10:03:00 +0000 (11:03 +0100)]
add comment and copy of pseudo-code for OP_RFID into trap proof_main_stage.py
Luke Kenneth Casson Leighton [Sat, 18 Jul 2020 09:48:37 +0000 (10:48 +0100)]
review of OP_RFID showed up some errors
Luke Kenneth Casson Leighton [Sat, 18 Jul 2020 09:07:25 +0000 (10:07 +0100)]
corrections to trap main_stage.py OP_RFID according to reading spec
Samuel A. Falvo II [Sat, 18 Jul 2020 04:09:52 +0000 (21:09 -0700)]
WIP: FV failing for unknown reasons.
Can someone put a second pair of eyes on this code? I don't understand
why FV is failing for the RFID instruction. I've spent at least three
hours trying to diagnose this without success.
Jacob Lifshay [Sat, 18 Jul 2020 03:17:40 +0000 (20:17 -0700)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
Jacob Lifshay [Sat, 18 Jul 2020 03:16:27 +0000 (20:16 -0700)]
add div fsm core (`DivState*`) with tests
comb test works
fsm test fails for some reason
Samuel A. Falvo II [Sat, 18 Jul 2020 01:00:05 +0000 (18:00 -0700)]
Failing test: fast1/fast2 vs srr0/srr1? on trap pipe
Samuel A. Falvo II [Sat, 18 Jul 2020 00:05:26 +0000 (17:05 -0700)]
forgot to clean up workspace in source
Samuel A. Falvo II [Sat, 18 Jul 2020 00:04:33 +0000 (17:04 -0700)]
FV props for SC instruction
Samuel A. Falvo II [Fri, 17 Jul 2020 23:26:23 +0000 (16:26 -0700)]
First FV property for trap unit
Jacob Lifshay [Fri, 17 Jul 2020 20:56:21 +0000 (13:56 -0700)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
Jacob Lifshay [Fri, 17 Jul 2020 20:55:26 +0000 (13:55 -0700)]
start adding FSMDivCore*
Luke Kenneth Casson Leighton [Fri, 17 Jul 2020 20:50:36 +0000 (21:50 +0100)]
comment explaining why not to call self.trap in PowerDecode2
Luke Kenneth Casson Leighton [Fri, 17 Jul 2020 19:42:27 +0000 (20:42 +0100)]
likewise cut across latest Minerva loadstore with line-for-line manual compare
Luke Kenneth Casson Leighton [Fri, 17 Jul 2020 19:35:09 +0000 (20:35 +0100)]
sigh easier to just do a line-for-line comparison of latest minerva fetch
Jacob Lifshay [Fri, 17 Jul 2020 19:30:11 +0000 (12:30 -0700)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
Luke Kenneth Casson Leighton [Fri, 17 Jul 2020 19:22:24 +0000 (20:22 +0100)]
port minerva cache fixes
commit
3a0158919144757a2b369c9b750c72339e912f1d
Author: Jean-François Nguyen <jf@lambdaconcept.com>
Date: Wed Sep 11 01:34:46 2019 +0200
fetch,loadstore: Fix `{f,m}_busy` signal in case of a cache miss.
Jacob Lifshay [Fri, 17 Jul 2020 19:19:33 +0000 (12:19 -0700)]
add .pylintrc
Luke Kenneth Casson Leighton [Fri, 17 Jul 2020 19:18:23 +0000 (20:18 +0100)]
forward-port minerva loadstore bugfix
commit
a03a72e04764dc976d85ea44b1cf0767e240b81f
Author: Jean-François Nguyen <jf@lambdaconcept.com>
Date: Thu Apr 30 12:23:36 2020 +0200
loadstore: fix conflict between write buffer and dcache refill.
Luke Kenneth Casson Leighton [Fri, 17 Jul 2020 18:58:48 +0000 (19:58 +0100)]
comments
Luke Kenneth Casson Leighton [Fri, 17 Jul 2020 18:47:09 +0000 (19:47 +0100)]
submodule update (again. sigh)
Luke Kenneth Casson Leighton [Fri, 17 Jul 2020 17:46:06 +0000 (18:46 +0100)]
whitespace
Luke Kenneth Casson Leighton [Fri, 17 Jul 2020 17:44:16 +0000 (18:44 +0100)]
use convenience vars in spr proof
Samuel A. Falvo II [Fri, 17 Jul 2020 17:30:10 +0000 (10:30 -0700)]
Flesh out SPR-related FV properties.
Luke Kenneth Casson Leighton [Fri, 17 Jul 2020 12:15:32 +0000 (13:15 +0100)]
whitespace
Luke Kenneth Casson Leighton [Fri, 17 Jul 2020 12:13:51 +0000 (13:13 +0100)]
whitespace
Jacob Lifshay [Fri, 17 Jul 2020 04:26:07 +0000 (21:26 -0700)]
add simulation-only division core using nmigen div and rem operators
Jacob Lifshay [Fri, 17 Jul 2020 03:07:18 +0000 (20:07 -0700)]
rename DIV->Div to be consistent
Jacob Lifshay [Fri, 17 Jul 2020 03:02:03 +0000 (20:02 -0700)]
format div code
Jacob Lifshay [Fri, 17 Jul 2020 02:43:18 +0000 (19:43 -0700)]
add missing fixedldstcache.py to .gitignore
Jacob Lifshay [Fri, 17 Jul 2020 02:39:06 +0000 (19:39 -0700)]
update submodule
Luke Kenneth Casson Leighton [Thu, 16 Jul 2020 10:24:09 +0000 (11:24 +0100)]
whoops tried doing mtspr priv, it failed but failed by trying to run TRAP
which is of course not in this pipeline
Luke Kenneth Casson Leighton [Thu, 16 Jul 2020 10:18:05 +0000 (11:18 +0100)]
get shiftrot compunit working
Luke Kenneth Casson Leighton [Thu, 16 Jul 2020 10:17:18 +0000 (11:17 +0100)]
more tidyup on use of CompOpSubsetBase
Luke Kenneth Casson Leighton [Thu, 16 Jul 2020 10:14:48 +0000 (11:14 +0100)]
use CompOpSubsetBase in ldst record