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note that traptype MUST increase in bitwidth corresponding to additions
2020-07-22
Luke Kenneth Casson...
note that traptype MUST increase in bitwidth corresponding...
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2020-07-22
Luke Kenneth Casson...
fix branch main_stage proof, add ctr 32-bit, fix BCREG
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2020-07-22
Luke Kenneth Casson...
rework branch proof to use br_input_record
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2020-07-22
Luke Kenneth Casson...
update README for pipe_data.py
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2020-07-22
Luke Kenneth Casson...
reduce number of FastRegs read ports
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2020-07-22
Luke Kenneth Casson...
comments on what goes into CommonPipeSpec
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2020-07-21
Luke Kenneth Casson...
convert branch pipeline to use msr/cia as immediates
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2020-07-21
Luke Kenneth Casson...
put set_msr and set_cia back in for now
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2020-07-21
Luke Kenneth Casson...
interesting bug in test_compunit.py when there are...
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2020-07-21
Luke Kenneth Casson...
testing if MultiCompUnit can handle no input regs ...
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2020-07-21
Luke Kenneth Casson...
disable cxxsim for now
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2020-07-21
Luke Kenneth Casson...
move cia and msr to trap input record
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2020-07-21
Luke Kenneth Casson...
set ISACaller.msr rather than namespace[MSR]
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2020-07-21
Luke Kenneth Casson...
when running an exception (trap) after "reset" must...
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2020-07-21
Luke Kenneth Casson...
spurious imports of FHDLTestCase, should be from nmutil
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2020-07-21
Luke Kenneth Casson...
whitespace
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2020-07-21
Luke Kenneth Casson...
add PC (CIA) to PowerDecode2 "state" for passing into...
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2020-07-21
Luke Kenneth Casson...
add msr exception bits setting function in hardware
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2020-07-21
Luke Kenneth Casson...
make cxxsim optional and print warning
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2020-07-21
Luke Kenneth Casson...
corrections to trap proof see
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2020-07-21
Luke Kenneth Casson...
use alias for msr_i in trap proof
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2020-07-21
Luke Kenneth Casson...
correct trap spec page interrupt ref
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2020-07-19
Luke Kenneth Casson...
do not start core in terminated mode
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2020-07-19
Luke Kenneth Casson...
explicitly set up a pc_i_ok signal in test_microwatt.py
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2020-07-19
Luke Kenneth Casson...
expose core_stop_i to outside as well
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2020-07-19
Luke Kenneth Casson...
set go_insn_i to non-resetless
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2020-07-19
Luke Kenneth Casson...
add issuer verilog generator
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2020-07-19
Luke Kenneth Casson...
update to expose signals at top-level of issuer
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2020-07-19
Luke Kenneth Casson...
convert compalu multi test to Simulator() (was run_simulation)
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2020-07-19
Luke Kenneth Casson...
convert compalu multi test to Simulator() (was run_simulation)
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2020-07-19
Luke Kenneth Casson...
use same write_vcd for cxxsim as pysim
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2020-07-19
Luke Kenneth Casson...
fix bug in alu_fsm.py found by cxxsim: missing one...
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2020-07-19
Luke Kenneth Casson...
add some CompUnit demo tests of the alu_fsm example
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2020-07-19
Luke Kenneth Casson...
move sdir to CompFSMOpSubset in alu_fsm example
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2020-07-19
Luke Kenneth Casson...
add CompFSMOpSubset, also change dir to sdir
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2020-07-19
Luke Kenneth Casson...
remove unneeded import
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2020-07-19
Luke Kenneth Casson...
if nmigen.sim.pysim import fails use nmigen.back.pysim
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2020-07-19
Luke Kenneth Casson...
use iocontrol PrevControl / NextControl instead of...
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2020-07-19
Luke Kenneth Casson...
add DivTestCase to test_issuer.py (commented out for...
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2020-07-18
Luke Kenneth Casson...
worked out that DivPipeSpec can be given a default...
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2020-07-18
Luke Kenneth Casson...
missing conversion of DIV to Div
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2020-07-18
Luke Kenneth Casson...
add option to generate verilog
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2020-07-18
Luke Kenneth Casson...
whoops use slice not range
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2020-07-18
Luke Kenneth Casson...
syntax error
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2020-07-18
Luke Kenneth Casson...
add SR latch cxxrtl backend demo
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2020-07-18
Luke Kenneth Casson...
add comment and copy of pseudo-code for OP_RFID into...
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2020-07-18
Luke Kenneth Casson...
review of OP_RFID showed up some errors
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2020-07-18
Luke Kenneth Casson...
corrections to trap main_stage.py OP_RFID according...
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2020-07-17
Luke Kenneth Casson...
comment explaining why not to call self.trap in PowerDecode2
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2020-07-17
Luke Kenneth Casson...
likewise cut across latest Minerva loadstore with line...
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2020-07-17
Luke Kenneth Casson...
sigh easier to just do a line-for-line comparison of...
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2020-07-17
Luke Kenneth Casson...
port minerva cache fixes
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2020-07-17
Luke Kenneth Casson...
forward-port minerva loadstore bugfix
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2020-07-17
Luke Kenneth Casson...
comments
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2020-07-17
Luke Kenneth Casson...
submodule update (again. sigh)
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2020-07-17
Luke Kenneth Casson...
whitespace
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2020-07-17
Luke Kenneth Casson...
use convenience vars in spr proof
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2020-07-17
Luke Kenneth Casson...
whitespace
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2020-07-17
Luke Kenneth Casson...
whitespace
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2020-07-16
Luke Kenneth Casson...
whoops tried doing mtspr priv, it failed but failed...
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2020-07-16
Luke Kenneth Casson...
get shiftrot compunit working
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2020-07-16
Luke Kenneth Casson...
more tidyup on use of CompOpSubsetBase
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2020-07-16
Luke Kenneth Casson...
use CompOpSubsetBase in ldst record
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2020-07-16
Luke Kenneth Casson...
sigh, bug in sprset.patch
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2020-07-16
Luke Kenneth Casson...
update cr input record to use new CompOpSubsetBase
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2020-07-16
Luke Kenneth Casson...
add regression test on setb simulator error
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2020-07-16
Luke Kenneth Casson...
use CompOpSubsetBase class in Branch op record
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2020-07-16
Luke Kenneth Casson...
get branch compunit working (missing bigendian arg)
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2020-07-16
Luke Kenneth Casson...
get trap compunit test working, adding bigendian and msr
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2020-07-16
Luke Kenneth Casson...
add mfmsr trap tests
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2020-07-15
Luke Kenneth Casson...
use new CompOpSubsetBase in trap
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2020-07-15
Luke Kenneth Casson...
remove unneeded comment in trap msin stage
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2020-07-15
Luke Kenneth Casson...
remove unneeded comment in trap pipe_data
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2020-07-15
Luke Kenneth Casson...
document branch pipeline relationship with PowerDecode2
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2020-07-15
Luke Kenneth Casson...
simplify instr_is_priv
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2020-07-15
Luke Kenneth Casson...
move traptype to soc.consts
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2020-07-15
Luke Kenneth Casson...
add better comments on mul overflow
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2020-07-15
Luke Kenneth Casson...
test privileged rfid call
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2020-07-15
Luke Kenneth Casson...
spelling error
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2020-07-15
Luke Kenneth Casson...
range of testing overflow was incorrect in mul
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2020-07-15
Luke Kenneth Casson...
set MSR up properly for privileged mtmsr test
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2020-07-15
Luke Kenneth Casson...
whoops forgot to update PC after trap in ISACaller
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2020-07-15
Luke Kenneth Casson...
move priv test to above illegal/trap test
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2020-07-15
Luke Kenneth Casson...
comments on IntegerData class
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2020-07-15
Luke Kenneth Casson...
import PipeContext not FPPipeContext
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2020-07-15
Luke Kenneth Casson...
minor reorg on PowerDecoder2, use switch/case rather...
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2020-07-15
Luke Kenneth Casson...
comments on SPRmap done in PowerDecode2
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2020-07-15
Luke Kenneth Casson...
comments on SPRmap done in PowerDecode2
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2020-07-15
Luke Kenneth Casson...
use case statement in PowerDecode2
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2020-07-15
Luke Kenneth Casson...
select RA based on LDSTMode.update in PowerDecode2
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2020-07-15
Luke Kenneth Casson...
add cache cx to LDSTMode
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2020-07-15
Luke Kenneth Casson...
remove unused class XerBits
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2020-07-15
Luke Kenneth Casson...
use Record Assert and also check muxid
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2020-07-15
Luke Kenneth Casson...
no need to check individual port members, just check...
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2020-07-14
Luke Kenneth Casson...
cookie-cut setup from alu proof_main_stage.py
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2020-07-14
Luke Kenneth Casson...
reduce code size by using CompOpSubsetBase for ALU...
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2020-07-14
Luke Kenneth Casson...
split out CompOpSubsetBase (meaning to do for a while)
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2020-07-14
Luke Kenneth Casson...
update docstrings
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2020-07-14
Luke Kenneth Casson...
adding MSR.PR unit test intended to activate privileged...
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2020-07-14
Luke Kenneth Casson...
attempting to access self.msr directly
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