| 2022-02-09 |
Luke Kenneth... | add opencores uart16550 instance wrapper |
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| 2022-02-01 |
Tobias Platen | correct path for make target microwatt_external_core |
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| 2022-01-31 |
Luke Kenneth... | fix bug in itlb_valid SRLatch set/reset, a bit weird... |
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| 2022-01-31 |
Luke Kenneth... | whoops tlb_valids in ICache is a combinatorial-get/set |
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| 2022-01-31 |
Luke Kenneth... | convert TLBValidArray in ICache to SRLatch |
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| 2022-01-31 |
Luke Kenneth... | add microwatt external core build target to Makefile |
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| 2022-01-31 |
Luke Kenneth... | use an SRLatch for cache_valids, at least it reduces... |
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| 2022-01-31 |
Luke Kenneth... | use Memory for cache tags in dcache |
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| 2022-01-31 |
Luke Kenneth... | use Memory for cache_tags in icache |
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| 2022-01-31 |
Luke Kenneth... | doh |
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| 2022-01-31 |
Luke Kenneth... | remove dummy trap pipeline |
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| 2022-01-31 |
Luke Kenneth... | remove combinatorial loop from MultiCompUnit |
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| 2022-01-30 |
Luke Kenneth... | break out cache_tags and cache_valids (again) this... |
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| 2022-01-30 |
Luke Kenneth... | remove CacheTagArray in icache.py |
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| 2022-01-30 |
Luke Kenneth... | create Memory for Cache Tags in I-Cache |
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| 2022-01-30 |
Luke Kenneth... | remove unneeded parameter |
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| 2022-01-30 |
Luke Kenneth... | add Array of CacheValids back in, so as to reduce LUT4... |
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| 2022-01-30 |
Luke Kenneth... | tagset is a local Signal in ICache |
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| 2022-01-30 |
Luke Kenneth... | identify combinatorial loop signals in MultiCompUnit... |
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| 2022-01-30 |
Luke Kenneth... | use nmigen Memory in I-Cache for TLB Lookups |
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| 2022-01-30 |
Luke Kenneth... | put itlb_valid back, ready for conversion to Memory... |
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| 2022-01-30 |
Luke Kenneth... | convert CacheRAM to Memory, acts much faster now |
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| 2022-01-29 |
Luke Kenneth... | explanatory comment when page hit is the same for stores |
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| 2022-01-29 |
Luke Kenneth... | use right offset in dcache wb address |
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| 2022-01-29 |
Luke Kenneth... | re-examining dcache.vhdl, still did not get the store... |
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| 2022-01-29 |
Luke Kenneth... | bug in dcache.py where when two stores occur in the... |
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| 2022-01-28 |
Luke Kenneth... | in LoadStore1 capture the address for misaligned dual... |
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| 2022-01-28 |
Luke Kenneth... | sort out misaligned store in LoadStore1 |
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| 2022-01-27 |
Luke Kenneth... | for second aligned request truncate address to nearest... |
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| 2022-01-25 |
Luke Kenneth... | add license and copyright header to dcache.py, |
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| 2022-01-25 |
Luke Kenneth... | LDSTException now passing bits of SRR1 around to the... |
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| 2022-01-24 |
Luke Kenneth... | comments |
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| 2022-01-24 |
Luke Kenneth... | hmm there seems to have been an error in DTLB Read, |
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| 2022-01-24 |
Luke Kenneth... | bool test on traptype to |
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| 2022-01-23 |
Luke Kenneth... | looked in soc.vhdl in microwatt and the parameters... |
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| 2022-01-23 |
Luke Kenneth... | add debug output of whether stall occurs on dcache |
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| 2022-01-22 |
Luke Kenneth... | missed setting of r0_full to zero in dcache. not encoun... |
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| 2022-01-21 |
Luke Kenneth... | skip ilang data in branch test_pipe_caller.py |
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| 2022-01-21 |
Luke Kenneth... | attempting to get compunit and test_pipe_caller unit... |
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| 2022-01-21 |
Luke Kenneth... | sigh, monitor DEC/TB StateRegs "properly" so that the... |
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| 2022-01-21 |
Luke Kenneth... | whoops fix bug in setting of DEC/TB (State) in test_core.py |
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| 2022-01-20 |
Luke Kenneth... | whoops MFSPR DEC/TB was reading from FastRegs not StateRegs |
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| 2022-01-19 |
Luke Kenneth... | whoops forgot to enable fast-reg read in DMI |
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| 2022-01-19 |
Luke Kenneth... | ISI (0x400) trap is the only one that puts memory-based... |
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| 2022-01-19 |
Luke Kenneth... | comments |
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| 2022-01-19 |
Luke Kenneth... | move DEC and TB into StateRegs, to make room in FastRegs |
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| 2022-01-18 |
Luke Kenneth... | add support for DMI debug read of FAST Regfile SPRs |
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| 2022-01-18 |
Luke Kenneth... | comments on SRR1 in trap |
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| 2022-01-18 |
Luke Kenneth... | preserve bits of SRR1 on a TRAP (including all interrup... |
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| 2022-01-17 |
Luke Kenneth... | fix hrfid and mtmsrd so that it is identical to microwatt |
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| 2022-01-17 |
Luke Kenneth... | connect up DEC/TB FSM pauser from core to Issuer |
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| 2022-01-17 |
Luke Kenneth... | comments |
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| 2022-01-17 |
Luke Kenneth... | whitespace |
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| 2022-01-17 |
Luke Kenneth... | add pause_dec_tb signal (not very sophisticated) to... |
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| 2022-01-17 |
Luke Kenneth... | add signal for pausing the DEC/TB FSM to IssuerBase |
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| 2022-01-16 |
Luke Kenneth... | raise interrupt on misaligned atomic LDST |
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| 2022-01-16 |
Luke Kenneth... | pass over store_done correctly from dcache over PortInt... |
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| 2022-01-16 |
Luke Kenneth... | add CR0 to LDSTCompUnit, for reporting if LR/SC store... |
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| 2022-01-16 |
Luke Kenneth... | remove PortInterface mmu_done signal, |
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| 2022-01-15 |
Luke Kenneth... | forgot name on dcache Reservation |
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| 2022-01-15 |
Luke Kenneth... | pass over atomic signals to dcache from loadstore. |
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| 2022-01-15 |
Luke Kenneth... | try using req.op in RELOAD_WAIT_ACK to detect whether... |
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| 2022-01-15 |
Luke Kenneth... | pass atomic reserve through from PortInterface to DCache |
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| 2022-01-15 |
Luke Kenneth... | add atomic LR/SC signal to LDSTCompUnit |
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| 2022-01-15 |
Luke Kenneth... | add reserve (atomic) signal to LDST data structures... |
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| 2022-01-15 |
Luke Kenneth... | tidyup PortInterface |
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| 2022-01-15 |
Luke Kenneth... | workaround for bug in dcache where the r1.req waiting... ldst_misalign |
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| 2022-01-15 |
Luke Kenneth... | enable both linux-5.7 tests |
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| 2022-01-14 |
Luke Kenneth... | split out CacheTag Record to separate structure |
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| 2022-01-14 |
Luke Kenneth... | update how d_valid is handled |
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| 2022-01-14 |
Luke Kenneth... | missed setting r1.store_way and r1.store_row in STORE_W... |
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| 2022-01-14 |
Luke Kenneth... | Revert "dcache 2nd stage (r1) should only indicate... |
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| 2022-01-14 |
Luke Kenneth... | second test for linux-5.7 |
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| 2022-01-12 |
Luke Kenneth... | add allow-overlap option to issuer_verilog.py |
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| 2022-01-12 |
Luke Kenneth... | dcache 2nd stage (r1) should only indicate not-busy |
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| 2022-01-12 |
Luke Kenneth... | fix issue with priv_mode not being passed correctly... |
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| 2022-01-12 |
Luke Kenneth... | fix issue with d_valid in dcache, was not being set... |
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| 2022-01-10 |
Luke Kenneth... | LoadStore1 priv_mode was not being correctly picked... |
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| 2022-01-09 |
Luke Kenneth... | grab the LDST request address for microwatt verilator... |
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| 2022-01-09 |
Luke Kenneth... | add linux-5.7 unit test which showed a silly error: |
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| 2022-01-08 |
Luke Kenneth... | fix MMU lookup after 2nd request (misaligned) by also... |
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| 2022-01-08 |
Luke Kenneth... | add microwatt mmu.bin test5 to show page-fault on misal... |
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| 2022-01-08 |
Luke Kenneth... | do not clear out ldst request after TLB entry is added |
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| 2022-01-08 |
Luke Kenneth... | enable microwatt mmu test2 |
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| 2022-01-08 |
Luke Kenneth... | whitespace and use exc is None not exc == None |
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| 2022-01-08 |
Luke Kenneth... | add a second LD request to dcache which is merged with... |
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| 2022-01-08 |
Luke Kenneth... | start adding in mis-aligned LD/ST support into LoadStore1 |
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| 2022-01-08 |
Tobias Platen | add function test_pi_ld_misalign |
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| 2022-01-07 |
Tobias Platen | begin testcase for misalign |
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| 2022-01-07 |
Luke Kenneth... | whitespace |
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| 2022-01-07 |
Luke Kenneth... | add missing MSRSpec import |
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| 2022-01-07 |
Luke Kenneth... | add msr_o to issuer in microwatt_compat mode |
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| 2022-01-06 |
Luke Kenneth... | double the number of lines in the L1 D/I-Cache to match... |
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| 2022-01-06 |
Luke Kenneth... | add SECOND_REQ state to loadstore.py, not yet implemented |
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| 2022-01-05 |
Luke Kenneth... | add easy-to-access debug reporting of instruction and PC |
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| 2022-01-05 |
Luke Kenneth... | use microwatt-specific PLRU due to bug in nmutil version |
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| 2022-01-04 |
Luke Kenneth... | fix DriverConflict over MSR write in Issuer/Core by... |
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| 2022-01-04 |
Luke Kenneth... | remove FetchFSM from TestIssuer (it served its purpose... |
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| 2022-01-03 |
Luke Kenneth... | doh, bus-hack was the wrong way round. *output* the... |
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| 2022-01-03 |
Luke Kenneth... | sigh, microwatts wishbone bus usage is non-wishbone... |
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