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soc.git
2021-12-23 Luke Kenneth... pass in msr_reset to issuer_verilog.py commit | commitdiff | tree
2021-12-23 Luke Kenneth... add ability to set the reset values of RegFileArray commit | commitdiff | tree
2021-12-23 Cesar StraussRemove extra wait on core_stop_o at end of Execute. commit | commitdiff | tree
2021-12-23 Cesar StraussRe-enable core stopped signal when stopped. commit | commitdiff | tree
2021-12-22 Luke Kenneth... only use a single variable for ack adjusting in dcache.py commit | commitdiff | tree
2021-12-22 Luke Kenneth... fix issues with running core in DMI "stopped" status... commit | commitdiff | tree
2021-12-22 Luke Kenneth... when setting DSISR in LoadStore1 use correct load bit... commit | commitdiff | tree
2021-12-22 Luke Kenneth... use correct X-Form L field in OP_MTMSRD commit | commitdiff | tree
2021-12-22 Luke Kenneth... check problem state in OP_MTMSRD from original reg... commit | commitdiff | tree
2021-12-22 Luke Kenneth... whoops, use MSR.IR for I-Cache fetch! commit | commitdiff | tree
2021-12-22 Luke Kenneth... remove unneeded state in LoadStore1 commit | commitdiff | tree
2021-12-22 Luke Kenneth... clear instruction fault on exception WAIT_MMU ACK in... commit | commitdiff | tree
2021-12-22 Luke Kenneth... clear out instr_fault when exception is thrown commit | commitdiff | tree
2021-12-22 Luke Kenneth... clear instruction fault on idle/valid in Loadstore1 commit | commitdiff | tree
2021-12-22 Luke Kenneth... ooo far too late at night to be doing this commit | commitdiff | tree
2021-12-22 Luke Kenneth... whoops use C not Const commit | commitdiff | tree
2021-12-22 Luke Kenneth... whoops use C not Const commit | commitdiff | tree
2021-12-22 Luke Kenneth... remove bus_ack (found bug in Simulation, sorted) commit | commitdiff | tree
2021-12-22 Luke Kenneth... bug in mmu setting radix tree size with one extra bit commit | commitdiff | tree
2021-12-21 Luke Kenneth... continue to assert PC in FetchFSM if needed commit | commitdiff | tree
2021-12-21 Luke Kenneth... enable I-Cache wishbone memory type in issuer_verilog... commit | commitdiff | tree
2021-12-21 Luke Kenneth... whoops issuer_verilog.py enabling mmu has to pass micro... commit | commitdiff | tree
2021-12-21 Luke Kenneth... for each unit test case in test_issuer_mmu_data_path... commit | commitdiff | tree
2021-12-21 Luke Kenneth... test_issuer_mmu_data_path.py needs to use wb_get because of commit | commitdiff | tree
2021-12-21 Luke Kenneth... mmu code-comments commit | commitdiff | tree
2021-12-21 Luke Kenneth... comments commit | commitdiff | tree
2021-12-21 Luke Kenneth... use prtbl in proc_tbl_wait in mmu commit | commitdiff | tree
2021-12-21 Luke Kenneth... mmu.py comments commit | commitdiff | tree
2021-12-20 Luke Kenneth... set up DAR correctly in unit tests, added set_ldst_spr... commit | commitdiff | tree
2021-12-20 Luke Kenneth... unit tests for SPRs when MMU enabled, commit | commitdiff | tree
2021-12-20 Luke Kenneth... more code-comments commit | commitdiff | tree
2021-12-20 Luke Kenneth... code-comments in MMU commit | commitdiff | tree
2021-12-20 Luke Kenneth... prefer not to invert when doing if/else. commit | commitdiff | tree
2021-12-20 Luke Kenneth... more code-comments commit | commitdiff | tree
2021-12-20 Luke Kenneth... add RTPDE - Radit Tree Page Directory Entry - Record... commit | commitdiff | tree
2021-12-20 Luke Kenneth... add (and ues) PRTBL Record in MMU commit | commitdiff | tree
2021-12-20 Luke Kenneth... create PGTBL Record and use it in MMU page_table_idle commit | commitdiff | tree
2021-12-19 Luke Kenneth... add hard stop address in ifetch unit test, bit of a... commit | commitdiff | tree
2021-12-19 Luke Kenneth... set terminate if core terminate requested commit | commitdiff | tree
2021-12-19 Luke Kenneth... code-comments commit | commitdiff | tree
2021-12-19 Luke Kenneth... add DMI STOPADDR register and use it in HDLRunner to... commit | commitdiff | tree
2021-12-19 Luke Kenneth... break out when core is stopped in HDLRunner commit | commitdiff | tree
2021-12-18 Luke Kenneth... add link to XICS bugreport commit | commitdiff | tree
2021-12-18 Luke Kenneth... sort out reset signalling after tracking down Simulatio... commit | commitdiff | tree
2021-12-18 Luke Kenneth... add icache/dcache/mmu unit test for TestIssuer commit | commitdiff | tree
2021-12-18 Luke Kenneth... get instructions to re-run in issuer after I-Cache... commit | commitdiff | tree
2021-12-18 Luke Kenneth... forgot to connect up I-Cache to MMU commit | commitdiff | tree
2021-12-18 Luke Kenneth... move connection of bus.stall in icache.py, commit | commitdiff | tree
2021-12-18 Luke Kenneth... tidyup commit | commitdiff | tree
2021-12-18 Luke Kenneth... tlb_req_index is TLB_BITS long not TLB_SIZE commit | commitdiff | tree
2021-12-16 Luke Kenneth... whoops, a Simulation bug, dcache bus ack Signal needed... commit | commitdiff | tree
2021-12-16 Luke Kenneth... give names to MMU records commit | commitdiff | tree
2021-12-16 Luke Kenneth... set_mmu_spr was using the slow-SPR index for the regfile commit | commitdiff | tree
2021-12-16 Luke Kenneth... whoops remove duplicate code (cut/paste error) no harm... commit | commitdiff | tree
2021-12-15 Luke Kenneth... remove more unneeded code commit | commitdiff | tree
2021-12-15 Luke Kenneth... read MSR.PR and MSR.DR and update ICache priv/virt... commit | commitdiff | tree
2021-12-15 Luke Kenneth... remove more of SVP64 from TestIssuerInternalInOrder commit | commitdiff | tree
2021-12-15 Luke Kenneth... remove update of pc, msr and svstate from TestIssuerInOrder commit | commitdiff | tree
2021-12-15 Luke Kenneth... move update of pc, msr and svstate into TestIssuerBase commit | commitdiff | tree
2021-12-15 Luke Kenneth... comment-out TestIssuerInternalInorder for now commit | commitdiff | tree
2021-12-15 Luke Kenneth... move alternative TestIssuerInternalInOrder to new file commit | commitdiff | tree
2021-12-15 Luke Kenneth... split out common elaboratable code from TestIssuer, commit | commitdiff | tree
2021-12-15 Luke Kenneth... big split-out of common functions in TestIssuer to... commit | commitdiff | tree
2021-12-15 Luke Kenneth... simplifying / tidyup of TestIssuer to get CoreState commit | commitdiff | tree
2021-12-15 Luke Kenneth... sort out MSR, read/write in same way as PC/SVSTATE... commit | commitdiff | tree
2021-12-15 Luke Kenneth... whoops accidentally commented out setup of instructions commit | commitdiff | tree
2021-12-15 Luke Kenneth... get fetch_failed working with no MMU commit | commitdiff | tree
2021-12-14 Tobias Platentest_loadstore1.py: test_loadstore1_ifetch_multi now... commit | commitdiff | tree
2021-12-14 Luke Kenneth... trying to get TestIssuer FSM to respond correctly to... commit | commitdiff | tree
2021-12-14 Luke Kenneth... get OP_FETCH_FAILED to respond/return an exception... commit | commitdiff | tree
2021-12-14 Luke Kenneth... update wb_get memory with instructions if required commit | commitdiff | tree
2021-12-14 Tobias Platenfix test_loadstore1_ifetch_multi() in test_loadstore1.py commit | commitdiff | tree
2021-12-14 Tobias Platenwip test case for virtual address fetch using fetch... commit | commitdiff | tree
2021-12-14 Tobias Platenfix test_loadstore1_ifetch_multi() commit | commitdiff | tree
2021-12-14 Jonathan NeuschäferGitLab-CI: Increase clone depth commit | commitdiff | tree
2021-12-14 Luke Kenneth... MMU LOOKUP for fetch failed, priv mode is inversion... commit | commitdiff | tree
2021-12-14 Luke Kenneth... link MSR.PR into MMU FSM OP_FETCH_FAILED commit | commitdiff | tree
2021-12-13 Luke Kenneth... return temporarily to older version of pinmux submodule commit | commitdiff | tree
2021-12-13 Luke Kenneth... request a flush of icache to clear the instruction... commit | commitdiff | tree
2021-12-13 Tobias Platentry to get multi test running commit | commitdiff | tree
2021-12-13 Tobias Platencomments about test_loadstore1_ifetch() commit | commitdiff | tree
2021-12-13 Luke Kenneth... fix test_loadstore1.py with MSR=PR/DR commit | commitdiff | tree
2021-12-13 Luke Kenneth... set pr=0 because privileged mode is pr=0 not pr=1 commit | commitdiff | tree
2021-12-13 Luke Kenneth... add in missing MSRSpec import commit | commitdiff | tree
2021-12-13 Luke Kenneth... commented-out code commit | commitdiff | tree
2021-12-13 Tobias Platenupdate MMU PortInterface Test (misalign) commit | commitdiff | tree
2021-12-13 Tobias Platencleanup test_ldst_pi.py commit | commitdiff | tree
2021-12-13 Tobias Platenupdate old TestMicrowattMemoryPortInterface commit | commitdiff | tree
2021-12-13 Tobias Platenreplace msr_pr with msr commit | commitdiff | tree
2021-12-13 Tobias Platencleanup test_dcbz_pi.py commit | commitdiff | tree
2021-12-13 Luke Kenneth... fix up pr/dr/sf in PortInterfaceBase commit | commitdiff | tree
2021-12-13 Luke Kenneth... pass in new MSRSpec to test_loadstore1.py not msr_pr=1 commit | commitdiff | tree
2021-12-13 Luke Kenneth... convert PortInterfaceBase to pass msr not msr_pr commit | commitdiff | tree
2021-12-13 Luke Kenneth... convert LoadStore1 to new msr.pr/dr/sf commit | commitdiff | tree
2021-12-13 Luke Kenneth... add msr to MMU Op Subset record commit | commitdiff | tree
2021-12-13 Tobias Platenuse NamedTuple pr in test_pi2ls commit | commitdiff | tree
2021-12-13 Luke Kenneth... still have to import MSRSpec commit | commitdiff | tree
2021-12-13 Luke Kenneth... connect up PortInterface priv_mode, virt_mode and mode_... commit | commitdiff | tree
2021-12-13 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org... commit | commitdiff | tree
2021-12-13 Luke Kenneth... construct an MSRSpec in PortInterfaceBase (not used... commit | commitdiff | tree
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