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missing ports from issuer, when doing verilog
[soc.git] / src /
2020-07-22 Luke Kenneth Casso... missing ports from issuer, when doing verilog tree | commitdiff
2020-07-22 Luke Kenneth Casso... add clock domain using snippet taken from random file tree | commitdiff
2020-07-22 Luke Kenneth Casso... cleanup in litex core.py tree | commitdiff
2020-07-22 Luke Kenneth Casso... update comments tree | commitdiff
2020-07-22 Luke Kenneth Casso... add dummy irq set/get tree | commitdiff
2020-07-22 Luke Kenneth Casso... add boot-helper.S etc from microwatt litex core tree | commitdiff
2020-07-22 Luke Kenneth Casso... set additional MSR bits according to v3.0B spec when... tree | commitdiff
2020-07-22 Luke Kenneth Casso... use (new) MSRb and PIb which has auto-bigendian numbers tree | commitdiff
2020-07-22 Luke Kenneth Casso... sigh, auto-create some little/big-endian classes for... tree | commitdiff
2020-07-22 Luke Kenneth Casso... missed import of Builder, set cpu_type to "None" tempor... tree | commitdiff
2020-07-22 Luke Kenneth Casso... begin converting litex sim to libre-soc tree | commitdiff
2020-07-22 Luke Kenneth Casso... whoops forgot field accessor tree | commitdiff
2020-07-22 Luke Kenneth Casso... do not use wildcard import tree | commitdiff
2020-07-22 Luke Kenneth Casso... start from vexriscv sim.py from tree | commitdiff
2020-07-22 Luke Kenneth Casso... correct syntax error tree | commitdiff
2020-07-22 Luke Kenneth Casso... first version of litex core (to be submitted upstream... tree | commitdiff
2020-07-22 Luke Kenneth Casso... whoops typo, 63-start not 3-start (doh) tree | commitdiff
2020-07-22 Luke Kenneth Casso... field number ordering wrong way round? tree | commitdiff
2020-07-22 Luke Kenneth Casso... syntax error tree | commitdiff
2020-07-22 Luke Kenneth Casso... review trap main_stage.py modifications: we are not... tree | commitdiff
2020-07-22 Luke Kenneth Casso... comments, add page spec numbers for branch ops into... tree | commitdiff
2020-07-22 Luke Kenneth Casso... add comment headings with spec page numbers tree | commitdiff
2020-07-22 Luke Kenneth Casso... comment on op.insn ordering tree | commitdiff
2020-07-22 Luke Kenneth Casso... code-shuffle, add comments tree | commitdiff
2020-07-22 Luke Kenneth Casso... add TT.size and use it in PowerDecoder and trap input... tree | commitdiff
2020-07-22 Luke Kenneth Casso... inline comments in trap proof tree | commitdiff
2020-07-22 Luke Kenneth Casso... note that traptype MUST increase in bitwidth correspond... tree | commitdiff
2020-07-22 Luke Kenneth Casso... fix branch main_stage proof, add ctr 32-bit, fix BCREG tree | commitdiff
2020-07-22 Luke Kenneth Casso... rework branch proof to use br_input_record tree | commitdiff
2020-07-22 Luke Kenneth Casso... update README for pipe_data.py tree | commitdiff
2020-07-22 Luke Kenneth Casso... reduce number of FastRegs read ports tree | commitdiff
2020-07-22 Luke Kenneth Casso... comments on what goes into CommonPipeSpec tree | commitdiff
2020-07-22 Samuel A. Falvo IIComplete FV properties for OP_TRAP instructions. tree | commitdiff
2020-07-22 Samuel A. Falvo IIPEP8 compliance tree | commitdiff
2020-07-22 Jacob Lifshayworking on FSMDivCoreStage tree | commitdiff
2020-07-22 Jacob Lifshayfix test_div_state_fsm tree | commitdiff
2020-07-21 Samuel A. Falvo IICompleted SC FV properties tree | commitdiff
2020-07-21 Samuel A. Falvo IIRefine properties to comply with spec tree | commitdiff
2020-07-21 Samuel A. Falvo IIFix where msr_i gets its value from tree | commitdiff
2020-07-21 Samuel A. Falvo IIMerge in recent updates to TRAP FV properties. tree | commitdiff
2020-07-21 Luke Kenneth Casso... convert branch pipeline to use msr/cia as immediates tree | commitdiff
2020-07-21 Luke Kenneth Casso... put set_msr and set_cia back in for now tree | commitdiff
2020-07-21 Luke Kenneth Casso... interesting bug in test_compunit.py when there are... tree | commitdiff
2020-07-21 Luke Kenneth Casso... testing if MultiCompUnit can handle no input regs ... tree | commitdiff
2020-07-21 Luke Kenneth Casso... disable cxxsim for now tree | commitdiff
2020-07-21 Luke Kenneth Casso... move cia and msr to trap input record tree | commitdiff
2020-07-21 Luke Kenneth Casso... set ISACaller.msr rather than namespace[MSR] tree | commitdiff
2020-07-21 Luke Kenneth Casso... when running an exception (trap) after "reset" must... tree | commitdiff
2020-07-21 Luke Kenneth Casso... spurious imports of FHDLTestCase, should be from nmutil tree | commitdiff
2020-07-21 Luke Kenneth Casso... whitespace tree | commitdiff
2020-07-21 Luke Kenneth Casso... add PC (CIA) to PowerDecode2 "state" for passing into... tree | commitdiff
2020-07-21 Luke Kenneth Casso... add msr exception bits setting function in hardware tree | commitdiff
2020-07-21 Luke Kenneth Casso... make cxxsim optional and print warning tree | commitdiff
2020-07-21 Luke Kenneth Casso... corrections to trap proof see tree | commitdiff
2020-07-21 Luke Kenneth Casso... use alias for msr_i in trap proof tree | commitdiff
2020-07-21 Luke Kenneth Casso... correct trap spec page interrupt ref tree | commitdiff
2020-07-20 Samuel A. Falvo IIRework SC properties to conform to style tree | commitdiff
2020-07-20 Samuel A. Falvo IIFormal properties for RFID. tree | commitdiff
2020-07-20 Cesar StraussDocument the move of sdir from data_i to op. tree | commitdiff
2020-07-20 Cesar StraussRemove extra yield from test case. tree | commitdiff
2020-07-19 Luke Kenneth Casso... do not start core in terminated mode tree | commitdiff
2020-07-19 Luke Kenneth Casso... explicitly set up a pc_i_ok signal in test_microwatt.py tree | commitdiff
2020-07-19 Luke Kenneth Casso... expose core_stop_i to outside as well tree | commitdiff
2020-07-19 Luke Kenneth Casso... set go_insn_i to non-resetless tree | commitdiff
2020-07-19 Luke Kenneth Casso... add issuer verilog generator tree | commitdiff
2020-07-19 Luke Kenneth Casso... update to expose signals at top-level of issuer tree | commitdiff
2020-07-19 Luke Kenneth Casso... convert compalu multi test to Simulator() (was run_simu... tree | commitdiff
2020-07-19 Luke Kenneth Casso... convert compalu multi test to Simulator() (was run_simu... tree | commitdiff
2020-07-19 Luke Kenneth Casso... use same write_vcd for cxxsim as pysim tree | commitdiff
2020-07-19 Luke Kenneth Casso... fix bug in alu_fsm.py found by cxxsim: missing one... tree | commitdiff
2020-07-19 Luke Kenneth Casso... add some CompUnit demo tests of the alu_fsm example tree | commitdiff
2020-07-19 Luke Kenneth Casso... move sdir to CompFSMOpSubset in alu_fsm example tree | commitdiff
2020-07-19 Luke Kenneth Casso... add CompFSMOpSubset, also change dir to sdir tree | commitdiff
2020-07-19 Luke Kenneth Casso... remove unneeded import tree | commitdiff
2020-07-19 Luke Kenneth Casso... if nmigen.sim.pysim import fails use nmigen.back.pysim tree | commitdiff
2020-07-19 Luke Kenneth Casso... use iocontrol PrevControl / NextControl instead of... tree | commitdiff
2020-07-19 Luke Kenneth Casso... add DivTestCase to test_issuer.py (commented out for... tree | commitdiff
2020-07-19 Cesar StraussImplement control path and unit test. tree | commitdiff
2020-07-18 Luke Kenneth Casso... worked out that DivPipeSpec can be given a default... tree | commitdiff
2020-07-18 Luke Kenneth Casso... missing conversion of DIV to Div tree | commitdiff
2020-07-18 Luke Kenneth Casso... add option to generate verilog tree | commitdiff
2020-07-18 Luke Kenneth Casso... whoops use slice not range tree | commitdiff
2020-07-18 Luke Kenneth Casso... syntax error tree | commitdiff
2020-07-18 Cesar StraussImplement the Shifter data path tree | commitdiff
2020-07-18 Cesar StraussDocument move of the next port data tree | commitdiff
2020-07-18 Luke Kenneth Casso... add SR latch cxxrtl backend demo tree | commitdiff
2020-07-18 Luke Kenneth Casso... add comment and copy of pseudo-code for OP_RFID into... tree | commitdiff
2020-07-18 Luke Kenneth Casso... review of OP_RFID showed up some errors tree | commitdiff
2020-07-18 Luke Kenneth Casso... corrections to trap main_stage.py OP_RFID according... tree | commitdiff
2020-07-18 Samuel A. Falvo IIWIP: FV failing for unknown reasons. tree | commitdiff
2020-07-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org... tree | commitdiff
2020-07-18 Jacob Lifshayadd div fsm core (`DivState*`) with tests tree | commitdiff
2020-07-18 Samuel A. Falvo IIFailing test: fast1/fast2 vs srr0/srr1? on trap pipe tree | commitdiff
2020-07-18 Samuel A. Falvo IIforgot to clean up workspace in source tree | commitdiff
2020-07-18 Samuel A. Falvo IIFV props for SC instruction tree | commitdiff
2020-07-17 Samuel A. Falvo IIFirst FV property for trap unit tree | commitdiff
2020-07-17 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org... tree | commitdiff
2020-07-17 Jacob Lifshaystart adding FSMDivCore* tree | commitdiff
2020-07-17 Luke Kenneth Casso... comment explaining why not to call self.trap in PowerDe... tree | commitdiff
2020-07-17 Luke Kenneth Casso... likewise cut across latest Minerva loadstore with line... tree | commitdiff
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