2021-12-22 |
Luke Kenneth Casso... | check problem state in OP_MTMSRD from original reg... |
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2021-05-04 |
Luke Kenneth Casso... | add SVSTATE (SVSRR0) to TRAP pipeline |
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2021-05-04 |
Luke Kenneth Casso... | adding fast3 SPR to Trap pipeline and unit test |
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2021-04-23 |
Luke Kenneth Casso... | more openpower-isa conversion |
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2021-04-23 |
Luke Kenneth Casso... | move over to from openpower imports |
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2020-10-06 |
Luke Kenneth Casso... | add SRR1 setting for LDST memory exception trap |
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2020-09-06 |
Luke Kenneth Casso... | comment, nothing unusual when Trap Type is DEC |
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2020-09-04 |
Luke Kenneth Casso... | adding option to include XICS external interrupts. |
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2020-08-14 |
Luke Kenneth Casso... | hack to get hrfid not to alter msr 51 |
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2020-07-27 |
Luke Kenneth Casso... | fix trap proof, and trap main_stage, and pseudocode... |
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2020-07-25 |
Luke Kenneth Casso... | update comment-headers (TODO include page numbers to... |
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2020-07-24 |
Samuel A. Falvo II | WIP: addressing code review, restoring proofs, etc. |
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2020-07-24 |
Luke Kenneth Casso... | got fed up with bit-slice ordering crap. cut it out |
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2020-07-24 |
Luke Kenneth Casso... | code review comments for trap and proof |
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2020-07-24 |
Samuel A. Falvo II | Refactorin of common code |
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2020-07-24 |
Samuel A. Falvo II | Address code review comments |
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2020-07-22 |
Luke Kenneth Casso... | field number ordering wrong way round? |
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2020-07-22 |
Luke Kenneth Casso... | review trap main_stage.py modifications: we are not... |
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2020-07-21 |
Samuel A. Falvo II | Completed SC FV properties |
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2020-07-21 |
Samuel A. Falvo II | Refine properties to comply with spec |
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2020-07-21 |
Luke Kenneth Casso... | move cia and msr to trap input record |
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2020-07-21 |
Luke Kenneth Casso... | add msr exception bits setting function in hardware |
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2020-07-21 |
Luke Kenneth Casso... | correct trap spec page interrupt ref |
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2020-07-18 |
Luke Kenneth Casso... | whoops use slice not range |
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2020-07-18 |
Luke Kenneth Casso... | syntax error |
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2020-07-18 |
Luke Kenneth Casso... | review of OP_RFID showed up some errors |
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2020-07-18 |
Luke Kenneth Casso... | corrections to trap main_stage.py OP_RFID according... |
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2020-07-15 |
Luke Kenneth Casso... | remove unneeded comment in trap msin stage |
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2020-07-15 |
Luke Kenneth Casso... | move traptype to soc.consts |
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2020-07-13 |
Luke Kenneth Casso... | add mtmsrd instruction and unit test |
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2020-07-12 |
Luke Kenneth Casso... | rename InternalOp to MicrOp |
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2020-07-08 |
Jacob Lifshay | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-07-06 |
Luke Kenneth Casso... | adding OP_MTMSR test |
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2020-07-05 |
Luke Kenneth Casso... | add mtmsr tests (fail) |
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2020-07-05 |
Luke Kenneth Casso... | check msr in trap test, fix OP_RFID |
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2020-07-04 |
Luke Kenneth Casso... | cater for illegal instruction (generates a trap) |
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2020-07-04 |
Luke Kenneth Casso... | add sc back in |
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2020-07-04 |
Luke Kenneth Casso... | comments in trap about exceptions using microcoding |
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2020-07-04 |
Luke Kenneth Casso... | update trap docstring |
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2020-07-04 |
Luke Kenneth Casso... | use new consts module |
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2020-07-01 |
Luke Kenneth Casso... | continue debugging trap pipeline |
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2020-07-01 |
Luke Kenneth Casso... | debugging trap pipeline |
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2020-07-01 |
Luke Kenneth Casso... | start running trap unit test, fixing errors |
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2020-06-09 |
Luke Kenneth Casso... | correct local variable references |
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2020-06-09 |
Luke Kenneth Casso... | bit more on TRAP handling (preparing priv instruction) |
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2020-06-08 |
Luke Kenneth Casso... | add traptype and trapaddr to PowerDecoder2. idea is... |
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2020-06-08 |
Luke Kenneth Casso... | found section in 3.0B PDF that refers to "Program Inter... |
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2020-06-08 |
Luke Kenneth Casso... | copy MSR into SRR1 in trap function |
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2020-06-08 |
colepoirier | Fix spelling |
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2020-06-07 |
Luke Kenneth Casso... | update trap with comments |
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2020-06-07 |
colepoirier | Add TrapMainStage.trap() convenience function to set... |
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2020-06-07 |
Luke Kenneth Casso... | move MSR_PR checking to separate functiong |
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2020-06-07 |
colepoirier | Fix missing 'comb +=' |
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2020-06-05 |
Luke Kenneth Casso... | update comments |
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2020-06-05 |
Luke Kenneth Casso... | more comments |
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2020-06-05 |
Luke Kenneth Casso... | more comments |
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2020-06-05 |
Luke Kenneth Casso... | a_i not b_in |
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2020-06-05 |
Luke Kenneth Casso... | add comments |
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2020-06-05 |
colepoirier | Made small changes to fu/trap/main_stage to bring nmige... |
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2020-06-05 |
Luke Kenneth Casso... | refer to srr0/1 not a/b |
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2020-06-05 |
Luke Kenneth Casso... | add msr_copy function and use it in OP_TRAP, OP_RFID... |
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2020-06-05 |
Luke Kenneth Casso... | set SRR0 in OP_SC |
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2020-06-04 |
colepoirier | Use a_i and b_i convenience variables instead of a... |
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2020-06-04 |
Luke Kenneth Casso... | mention convenience variables |
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2020-06-04 |
Luke Kenneth Casso... | rename trap to use convenience variables |
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2020-06-04 |
colepoirier | Undo damage done by deleting VHDL microwatt comments, |
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2020-06-03 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-06-03 |
colepoirier | Fixed missing nia.ok.eq(1) in OP_RFID |
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2020-06-03 |
colepoirier | Fixed merge conflict by using remote changes |
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2020-06-03 |
Luke Kenneth Casso... | convenience variables |
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2020-06-03 |
Luke Kenneth Casso... | FormX not FormXL |
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2020-06-03 |
Luke Kenneth Casso... | add bit more TODO |
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2020-06-03 |
Luke Kenneth Casso... | add more TODOs |
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2020-06-03 |
colepoirier | Fixed OP_RFID and OP_SC in fu/trap/main_stage |
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2020-06-03 |
Luke Kenneth Casso... | add some more constants and ref to POWER9 pdf |
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2020-06-03 |
Luke Kenneth Casso... | add an if for OP_MTMSR and some comments |
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2020-06-03 |
colepoirier | Attempted to fix OP_RFID in TRAP pipeline |
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2020-06-02 |
colepoirier | Implement TRAP instructions OP_RFID and OP_SC |
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2020-06-02 |
Luke Kenneth Casso... | add MSR constants, TODO translated |
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2020-06-02 |
Luke Kenneth Casso... | add TODO comments from microwatt source code |
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2020-05-27 |
Luke Kenneth Casso... | code-morph, add TODO on OP_RFID, OP_SC, OP_ADDPCIS |
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2020-05-24 |
Luke Kenneth Casso... | copy code for MTMSR from microwatt into comments |
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2020-05-24 |
Luke Kenneth Casso... | add links for trap main stage |
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2020-05-24 |
Luke Kenneth Casso... | add untested OP_MTMSR and OP_MFMSR |
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2020-05-24 |
Luke Kenneth Casso... | TODO mention OP_MTMSR/OP_MFMSR |
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2020-05-21 |
Luke Kenneth Casso... | add dedicated TrapPipeSpec |
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2020-05-19 |
Luke Kenneth Casso... | rename module, remove extraneous code and imports |
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2020-05-19 |
Luke Kenneth Casso... | hmmm, branch sets nia to Data as well and sets nia... |
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2020-05-19 |
Luke Kenneth Casso... | use Data on SPRs in Trap InputData just like in BranchO... |
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2020-05-19 |
Luke Kenneth Casso... | code-munge |
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2020-05-19 |
Michael Nolan | Add should_trap signal to trap output data |
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2020-05-19 |
Michael Nolan | Add trap main stage |
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2020-05-19 |
Michael Nolan | Begin adding trap FU |
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