2021-04-23 |
Luke Kenneth Casso... | submodule update |
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2021-04-18 |
Luke Kenneth Casso... | give spblock512 a name as a submodule |
tree | commitdiff |
2021-04-18 |
Luke Kenneth Casso... | rename SPBlock_512W64B8W to lowercase |
tree | commitdiff |
2021-04-18 |
Luke Kenneth Casso... | submodule update |
tree | commitdiff |
2021-04-18 |
Luke Kenneth Casso... | submodule update |
tree | commitdiff |
2021-04-18 |
Luke Kenneth Casso... | submodule update |
tree | commitdiff |
2021-04-16 |
Luke Kenneth Casso... | submodule update |
tree | commitdiff |
2021-04-08 |
Luke Kenneth Casso... | submodule update |
tree | commitdiff |
2021-04-06 |
Luke Kenneth Casso... | git submodule update |
tree | commitdiff |
2021-04-05 |
Luke Kenneth Casso... | litex submodule update |
tree | commitdiff |
2021-04-01 |
Luke Kenneth Casso... | git submodule update |
tree | commitdiff |
2021-04-01 |
Luke Kenneth Casso... | add soc-cocotb-sim submodule |
tree | commitdiff |
2021-04-01 |
Luke Kenneth Casso... | submodule update |
tree | commitdiff |
2021-04-01 |
Staf Verhaegen | libresoc-litex submodule update |
tree | commitdiff |
2021-04-01 |
Staf Verhaegen | libresoc-litex submodule update |
tree | commitdiff |
2021-03-30 |
Alain D D Williams | Merge branch 'master' of git.libre-soc.org:soc |
tree | commitdiff |
2021-03-30 |
Luke Kenneth Casso... | corrections to Makefile for building / not-building... |
tree | commitdiff |
2021-03-29 |
Luke Kenneth Casso... | update submodule |
tree | commitdiff |
2021-03-28 |
Luke Kenneth Casso... | reduce regfile port usage on non-svp64 |
tree | commitdiff |
2021-03-22 |
Luke Kenneth Casso... | add very small dff sram variant (no 4k SRAMs) |
tree | commitdiff |
2021-03-13 |
Luke Kenneth Casso... | include SVSTATE in namespace, passing to ISACaller |
tree | commitdiff |
2021-03-12 |
Luke Kenneth Casso... | remove old code |
tree | commitdiff |
2021-03-12 |
Luke Kenneth Casso... | remove old code |
tree | commitdiff |
2021-03-12 |
Luke Kenneth Casso... | remove old code |
tree | commitdiff |
2021-03-06 |
Luke Kenneth Casso... | add SPBlock_512W64B8W.v blackbox file |
tree | commitdiff |
2021-03-05 |
Luke Kenneth Casso... | remove sram4k wishbone bte/cti in litex interconnect |
tree | commitdiff |
2021-02-20 |
Luke Kenneth Casso... | add litex wishbone interconnect to 4x 4k SRAMs |
tree | commitdiff |
2020-12-06 |
Luke Kenneth Casso... | attempt to split into two separate GPIO banks due to... |
tree | commitdiff |
2020-12-03 |
Luke Kenneth Casso... | put ls180 litex bus width back to 32 bit temporarily |
tree | commitdiff |
2020-12-03 |
Luke Kenneth Casso... | argh issue with yosys ABC |
tree | commitdiff |
2020-12-03 |
Luke Kenneth Casso... | add 3 more 4k SRAMs, change WB bus width to 64 in ls180... |
tree | commitdiff |
2020-11-22 |
Luke Kenneth Casso... | simplify litex-core wishbone interfaces |
tree | commitdiff |
2020-11-14 |
Luke Kenneth Casso... | sigh, direction wrong in IOtypes litex core |
tree | commitdiff |
2020-11-13 |
Luke Kenneth Casso... | reduce number of nc in ls180 to 24 |
tree | commitdiff |
2020-11-13 |
Luke Kenneth Casso... | reduce clkcsel ls180 width (2 pins), rename pll_18... |
tree | commitdiff |
2020-11-13 |
Luke Kenneth Casso... | rename and add pll lock signal to ls180 |
tree | commitdiff |
2020-11-13 |
Luke Kenneth Casso... | rename ls180 litex pll_48 output to pll_18 |
tree | commitdiff |
2020-11-13 |
Luke Kenneth Casso... | remove io_in/out now it is not needed for niolib |
tree | commitdiff |
2020-11-10 |
Luke Kenneth Casso... | add build commands to Makefile for versa ecp5 |
tree | commitdiff |
2020-11-06 |
Luke Kenneth Casso... | sigh sorting out litex pin-connections to sdram |
tree | commitdiff |
2020-11-04 |
Luke Kenneth Casso... | move back to 3.3v on X3 VERSA ECP5 connector |
tree | commitdiff |
2020-11-03 |
Luke Kenneth Casso... | swap jtag pinorder to match ulx3s |
tree | commitdiff |
2020-11-03 |
Luke Kenneth Casso... | change LVCMOS level on versa ecp5 jtag to 2.5v |
tree | commitdiff |
2020-10-31 |
Cole Poirier | versa_ecp5.py add 4 arbitrarily assigned gpio pins... |
tree | commitdiff |
2020-10-30 |
Luke Kenneth Casso... | add JTAG extension to versa_ecp5 then we can use it |
tree | commitdiff |
2020-10-21 |
Cole Poirier | versa_ecp5 adds ability to build and load for ulx3s85f... |
tree | commitdiff |
2020-10-15 |
Luke Kenneth Casso... | add commented-out connection to JTAG in ECP5 litex |
tree | commitdiff |
2020-10-15 |
Luke Kenneth Casso... | add extra variant to litex core |
tree | commitdiff |
2020-10-15 |
Luke Kenneth Casso... | syntax error |
tree | commitdiff |
2020-10-15 |
Luke Kenneth Casso... | disable gpio in litex core |
tree | commitdiff |
2020-10-15 |
Luke Kenneth Casso... | enable/disable litex irqs based on variant name |
tree | commitdiff |
2020-10-12 |
Cole Poirier | litex/florent/versa_ecp5.py add arg --fpga [versa_ecp5... |
tree | commitdiff |
2020-10-12 |
Cole Poirier | add tested working fpga compile/build/load file for... |
tree | commitdiff |
2020-10-11 |
Luke Kenneth Casso... | record commands for building ECP5 |
tree | commitdiff |
2020-10-10 |
Cole Poirier | florent/versa_ecp5.py remove uneccessary imports, speci... |
tree | commitdiff |
2020-10-06 |
Luke Kenneth Casso... | add sdr bypass routing via JTAG boundary scan |
tree | commitdiff |
2020-10-04 |
Luke Kenneth Casso... | significant reorg of the litex pinspecs to use pinmux... |
tree | commitdiff |
2020-10-04 |
Luke Kenneth Casso... | remove ls180io import |
tree | commitdiff |
2020-10-04 |
Luke Kenneth Casso... | move ls180io.py back into ls180.py |
tree | commitdiff |
2020-10-03 |
Luke Kenneth Casso... | allow i2c to be routed via JTAG |
tree | commitdiff |
2020-10-03 |
Luke Kenneth Casso... | nope. put it back and connect to platform pads in... |
tree | commitdiff |
2020-10-03 |
Luke Kenneth Casso... | move iopad litex creation to ls180soc.py |
tree | commitdiff |
2020-10-01 |
Luke Kenneth Casso... | add clksel, pll to ls180 |
tree | commitdiff |
2020-09-30 |
Luke Kenneth Casso... | add I2C into ls180 |
tree | commitdiff |
2020-09-30 |
Luke Kenneth Casso... | add ASIC version of I2C Master |
tree | commitdiff |
2020-09-28 |
Luke Kenneth Casso... | reduce not-connected IO pins |
tree | commitdiff |
2020-09-28 |
Luke Kenneth Casso... | connect SDRAM dqm to wrdata_mask |
tree | commitdiff |
2020-09-28 |
Luke Kenneth Casso... | lots of sorting out iopads |
tree | commitdiff |
2020-09-28 |
Luke Kenneth Casso... | rewrite ilang file after litex ls180 build |
tree | commitdiff |
2020-09-27 |
Luke Kenneth Casso... | add Makefile for creating ls180.il |
tree | commitdiff |
2020-09-26 |
Luke Kenneth Casso... | DMI-to-JTAG needed to be "sync" to get ack/resp right |
tree | commitdiff |
2020-09-26 |
Luke Kenneth Casso... | try svf test of DMI MSR |
tree | commitdiff |
2020-09-26 |
Luke Kenneth Casso... | add ls180io.py |
tree | commitdiff |
2020-09-26 |
Luke Kenneth Casso... | get openocd svf test running, replicating jtag test |
tree | commitdiff |
2020-09-26 |
Luke Kenneth Casso... | add openocd configs |
tree | commitdiff |
2020-09-26 |
Luke Kenneth Casso... | reduce sdram pins to smaller address and only 1 cs_n |
tree | commitdiff |
2020-09-26 |
Luke Kenneth Casso... | only enable pads connections for ls180 for now |
tree | commitdiff |
2020-09-24 |
Luke Kenneth Casso... | do not have to use uart_litex gpio_litex names |
tree | commitdiff |
2020-09-24 |
Luke Kenneth Casso... | enable GPIO pads through C4M JTAG |
tree | commitdiff |
2020-09-24 |
Luke Kenneth Casso... | c4m iopad integration working |
tree | commitdiff |
2020-09-23 |
Luke Kenneth Casso... | cs_n and cke in sdram need to match in length |
tree | commitdiff |
2020-09-23 |
Luke Kenneth Casso... | change litex sdram pinouts to ASIC type |
tree | commitdiff |
2020-09-23 |
Luke Kenneth Casso... | redo litex SDCard to send out data/cmd o/i/en pins |
tree | commitdiff |
2020-09-23 |
Luke Kenneth Casso... | sort out GPIO with i/o/oe in ls180 |
tree | commitdiff |
2020-09-23 |
Luke Kenneth Casso... | add ls180 pinmap text file |
tree | commitdiff |
2020-09-23 |
Luke Kenneth Casso... | attempt GPIO bi-directional |
tree | commitdiff |
2020-09-23 |
Luke Kenneth Casso... | add I2C master to ls180 |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | add 2 PWMs (quick, easy to do) |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | move dmi_sim to separate module |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | add openocd.cfg experiment |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | create a JTAG platform and connect it up. jtagremote... |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | add jtagremote to litex sim, add new "variant" to core... |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | link litex ls180soc JTAG pads |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | add jtag wishbone and jtag ports to libresoc litex... |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | add sys_rst to Clock Reset Generator |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | add JTAG IOpads and rename rst to sys_rst |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | add similar platforms to ls180.py |
tree | commitdiff |
2020-09-19 |
Luke Kenneth Casso... | add pc_o not connected |
tree | commitdiff |
2020-09-19 |
Luke Kenneth Casso... | set ROM to empty, set SRAM to tiny 0x200, get things... |
tree | commitdiff |
2020-09-19 |
Luke Kenneth Casso... | urk. wishbone slave devices declared incorrectly (I... semi_working_ecp5 |
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