2020-09-06 |
Luke Kenneth Casso... | add reset option to Register |
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2020-09-06 |
Luke Kenneth Casso... | add unit test for slow SPRs (SPRG0/1) |
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2020-09-06 |
Luke Kenneth Casso... | minor code-munge on SPR-to-FAST mapping |
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2020-09-06 |
Luke Kenneth Casso... | move DEC and TB from StateRegs to FastRegs for several... |
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2020-09-06 |
Luke Kenneth Casso... | add DEC and TB to State regfile |
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2020-08-31 |
Luke Kenneth Casso... | add XER to fastregs and "construct" it in mfspr/mtspr |
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2020-08-25 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
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2020-08-25 |
Luke Kenneth Casso... | add CR read to DMI interface |
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2020-08-15 |
Luke Kenneth Casso... | rather big change to interaction between regfile and... |
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2020-08-14 |
Luke Kenneth Casso... | put multi-ports back (for read) on int and fast regfiles |
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2020-08-13 |
Luke Kenneth Casso... | add forwarding-bus mode to Regfile Memory (and disable it) |
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2020-08-13 |
Luke Kenneth Casso... | sigh. convert Fast regfile to binary |
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2020-08-13 |
Luke Kenneth Casso... | sigh. convert INT regfile to binary addressing |
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2020-08-13 |
Luke Kenneth Casso... | create a RegFileMem class that uses Memory |
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2020-08-11 |
Luke Kenneth Casso... | sigh, remove yet another int regfile read port |
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2020-08-11 |
Luke Kenneth Casso... | reduce regfile port usage for INT and FAST |
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2020-08-11 |
Luke Kenneth Casso... | reduce regfile ports by creating separate STATE regfile |
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2020-08-11 |
Luke Kenneth Casso... | reducing regfile port usage by sharing read ports |
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2020-08-03 |
Luke Kenneth Casso... | add extra port for debug read of int regs via DMI |
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2020-07-29 |
Jacob Lifshay | add __init__.py to all source directories |
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2020-07-22 |
Jacob Lifshay | Merge remote-tracking branch 'origin/master' |
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2020-07-22 |
Jacob Lifshay | format code |
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2020-07-22 |
Luke Kenneth Casso... | reduce number of FastRegs read ports |
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2020-07-14 |
Luke Kenneth Casso... | add MSR reading to issue FSM |
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2020-07-08 |
Luke Kenneth Casso... | adding in ALU test back in, debugging SPR setup |
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2020-07-08 |
Luke Kenneth Casso... | sorting out setting of XER |
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2020-07-08 |
Luke Kenneth Casso... | add spr to fast reg converter |
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2020-07-08 |
Jacob Lifshay | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-07-05 |
Luke Kenneth Casso... | add slow spr regfile regspec support |
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2020-07-04 |
Luke Kenneth Casso... | more rename spr1/spr2 to fast1/fast2 |
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2020-07-04 |
Luke Kenneth Casso... | add gitignores |
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2020-07-04 |
Luke Kenneth Casso... | debugging decoding of SPRs (fast) |
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2020-06-18 |
Jacob Lifshay | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-06-18 |
Luke Kenneth Casso... | slightly hacky way to keep an eye on the PC |
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2020-06-16 |
Luke Kenneth Casso... | add test instruction memory SRAM |
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2020-06-05 |
Luke Kenneth Casso... | name regfile ports by name not numerical position |
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2020-06-05 |
Luke Kenneth Casso... | whoops connecting up CR in wrong order. fixing with... |
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2020-06-05 |
Luke Kenneth Casso... | fix syntax errors and use correct FastRegs (SRR0/1... |
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2020-06-04 |
Luke Kenneth Casso... | initialise XER from simulation |
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2020-06-04 |
Luke Kenneth Casso... | add extra argument (not used) to regfile.py |
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2020-06-04 |
Luke Kenneth Casso... | use copy of FHDLTestCase |
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2020-06-04 |
Luke Kenneth Casso... | missing a fastregs write-port |
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2020-06-03 |
Luke Kenneth Casso... | connect read-enable and src_i to regfile ports |
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2020-06-03 |
Luke Kenneth Casso... | start putting a non-production core together, |
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2020-06-03 |
Luke Kenneth Casso... | decide to elaborate Refiles *into* another class, rathe... |
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2020-06-03 |
Luke Kenneth Casso... | turn RegFiles into module, add all regfiles to it |
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2020-06-03 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-06-03 |
Luke Kenneth Casso... | add class containing all regfiles |
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2020-06-03 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-06-02 |
Luke Kenneth Casso... | decode fast spr for OP_BCREG CTR, TAR and LR |
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2020-06-02 |
Luke Kenneth Casso... | whoops cut/paste error, creating write_ports not read_ports |
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2020-06-01 |
Michael Nolan | Add proof for RegFile |
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2020-06-01 |
Michael Nolan | Add proof for RegFileArray |
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2020-06-01 |
Michael Nolan | Have regfile use AnySeq instead of AnyConst |
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2020-06-01 |
Michael Nolan | Enable k-induction for register file proof |
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2020-06-01 |
Michael Nolan | That was weird. For some reason it wasn't generating... |
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2020-06-01 |
Michael Nolan | Full BMC proof of Register |
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2020-06-01 |
Michael Nolan | Begin rewrite of proof_regfile.py |
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2020-05-29 |
Luke Kenneth Casso... | interesting. use of Settle() works, showing that Regfi... |
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2020-05-28 |
Luke Kenneth Casso... | messing about with proof_regfile.py |
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2020-05-28 |
colepoirier | Added Initial() synchronous check with draft truth |
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2020-05-28 |
Luke Kenneth Casso... | hmm.... |
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2020-05-28 |
colepoirier | Add sync Assert for _wrports 'wen' signal in proof_regf... |
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2020-05-27 |
Luke Kenneth Casso... | do not use range(0, x) - just range(x) |
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2020-05-27 |
Luke Kenneth Casso... | remove write-block on register zero |
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2020-05-27 |
colepoirier | Derive proof_regfile Driver from regfile.Register(... |
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2020-05-27 |
colepoirier | Fix indentation of regfile/formal/proof_regfile.py |
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2020-05-27 |
colepoirier | First commit of proof of regfile, not working yet |
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2020-05-27 |
Luke Kenneth Casso... | add extra INT regs port for now, add Fast Regfile |
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2020-05-27 |
Luke Kenneth Casso... | added XER and CR regfiles, using new VirtualRegPort |
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2020-05-26 |
Luke Kenneth Casso... | check assertions |
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2020-05-26 |
Luke Kenneth Casso... | make read/write regs properly internal |
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2020-05-26 |
Luke Kenneth Casso... | add VirtualRegPort test, seems to demonstrate it working |
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2020-05-26 |
Luke Kenneth Casso... | remove sync (not needed) |
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2020-05-26 |
Luke Kenneth Casso... | get score6600_multi.py working again |
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2020-05-26 |
Luke Kenneth Casso... | redo focus of virtual reg port to do only full datawidt... |
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2020-05-26 |
Luke Kenneth Casso... | sort-of (maybe) implemented a virtual port on top of... |
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2020-05-26 |
Luke Kenneth Casso... | try new variant of VirtualRegFile |
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2020-05-26 |
Luke Kenneth Casso... | use nmutil treereduce |
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2020-05-26 |
Luke Kenneth Casso... | continue virtual regfile port |
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2020-05-26 |
colepoirier | First attempt at implementing block access rd and wr... |
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2020-05-25 |
Luke Kenneth Casso... | correct links in regfile docstring |
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2020-05-25 |
Luke Kenneth Casso... | document regfiles |
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2020-05-25 |
Luke Kenneth Casso... | add INT, SPR and CR regfiles |
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2020-05-24 |
Luke Kenneth Casso... | add stub regfiles.py |
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2020-03-09 |
Luke Kenneth Casso... | move all source directories to soc so that "import... |
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