continue mul unit test debugging
[soc.git] / src / soc / simple /
2020-07-05 Luke Kenneth Casso... big reorg on PowerDecoder2, actually Decode2Execute1Type
2020-07-05 Luke Kenneth Casso... add SPR test case, commented out for now
2020-07-05 Luke Kenneth Casso... move valid signal out of Decode2ToExecute1Type and...
2020-07-05 Luke Kenneth Casso... add slow spr regfile regspec support
2020-07-04 Luke Kenneth Casso... add pspec to test_core.py
2020-07-04 Luke Kenneth Casso... add pspec to test_core.py
2020-07-02 Luke Kenneth Casso... allow flexible selection of the types of ALUs
2020-07-02 Luke Kenneth Casso... add bare wishbone option to TestIssuer, sort out ports
2020-07-02 Luke Kenneth Casso... use single-arg pspec for TestIssuer and Core
2020-07-01 Luke Kenneth Casso... add name "test_issuer" to ilang conversion
2020-06-29 Luke Kenneth Casso... fetch instructions from bare wishbone fetch unit
2020-06-28 Luke Kenneth Casso... read from instruction memory using FetchUnitInterface
2020-06-28 Luke Kenneth Casso... expand instruction bus width to 64 bit, start on a...
2020-06-27 Luke Kenneth Casso... make PortInterface modules consistent with same API
2020-06-23 Luke Kenneth Casso... TstL0CacheBuffer returns array of ports differently now
2020-06-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-18 Luke Kenneth Casso... enable general test cases in test_issuer
2020-06-18 Luke Kenneth Casso... got loop example operational by noting when PC fastreg...
2020-06-18 Luke Kenneth Casso... use different way to pass instructions to test_issuer...
2020-06-18 Luke Kenneth Casso... debugging test_issuer.py general test cases
2020-06-18 Luke Kenneth Casso... slightly hacky way to keep an eye on the PC
2020-06-18 Luke Kenneth Casso... whoops generate core ilang not TestIssuer
2020-06-17 Luke Kenneth Casso... split out TestIssuer into separate module
2020-06-17 Luke Kenneth Casso... remove unneeded yield
2020-06-17 Luke Kenneth Casso... enable all tests again in test_core.py and test_issuer.py
2020-06-17 Luke Kenneth Casso... got test_issuer FSM operating. bit of a hack
2020-06-17 Luke Kenneth Casso... debugging test_issuer, getting FSM working
2020-06-17 Luke Kenneth Casso... output to issuer_simulator.vcd
2020-06-16 Luke Kenneth Casso... add first version unit test for TestIssuer
2020-06-16 Luke Kenneth Casso... reduce instruction depth to 6 bits in TestIssuer
2020-06-16 Luke Kenneth Casso... move debug statements to check function
2020-06-16 Luke Kenneth Casso... hack LD/ST ad/st together, allow PC to be set externally
2020-06-16 Luke Kenneth Casso... move check regs in simple core to separate function
2020-06-16 Luke Kenneth Casso... move test core reg set up into separate function
2020-06-16 Luke Kenneth Casso... set up a TestIssuer class with a FSM for doing instruct...
2020-06-16 Luke Kenneth Casso... add beginnings of TestIssuer class, to issue instructio...
2020-06-16 Luke Kenneth Casso... weird: adding TestMemory with no port causes nmigen...
2020-06-16 Luke Kenneth Casso... refer to signals directly in Test Core
2020-06-16 Luke Kenneth Casso... add test instruction memory SRAM
2020-06-15 Luke Kenneth Casso... have to set up addr/st rel-go link before setting up...
2020-06-15 Luke Kenneth Casso... add in memory setup/check but disable LDST Unit Tests...
2020-06-15 Luke Kenneth Casso... whoops LDSTCompUnit was identified as a Function.ALU...
2020-06-15 Luke Kenneth Casso... add in TstL0CacheBuffer but disable temporarily
2020-06-10 Luke Kenneth Casso... code-morph regspecmap functions, split into separate...
2020-06-08 Luke Kenneth Casso... re-add unit tests back in
2020-06-08 Luke Kenneth Casso... more verbose debug information tracking down SO/OV...
2020-06-08 Luke Kenneth Casso... code-morph test_core for XER bit clarity
2020-06-08 Luke Kenneth Casso... added check which shows that OV32 in "adde." is not...
2020-06-07 Luke Kenneth Casso... assert XER SO/OV/CA registers, check these are ok ...
2020-06-07 Luke Kenneth Casso... add debug print statements, re-enable all tests in...
2020-06-07 Luke Kenneth Casso... add msr to ISA in test_core.py
2020-06-06 Luke Kenneth Casso... missing test.mem arg for ISA in test_core
2020-06-05 Luke Kenneth Casso... comment out CR assertion for now
2020-06-05 Luke Kenneth Casso... experimenting with CR, not quite right
2020-06-05 Luke Kenneth Casso... name regfile ports by name not numerical position
2020-06-05 Luke Kenneth Casso... whoops connecting up CR in wrong order. fixing with...
2020-06-04 Luke Kenneth Casso... testing CRs after writing: not in the right bit-order
2020-06-04 Luke Kenneth Casso... remove unneeded code
2020-06-04 Luke Kenneth Casso... add branch test case to core
2020-06-04 Luke Kenneth Casso... no global variables in test suites
2020-06-04 Luke Kenneth Casso... sigh. because POWER. CR index inversion
2020-06-04 Luke Kenneth Casso... sigh. weirdness involving bit-inversion, inconsistency...
2020-06-04 Luke Kenneth Casso... no global variables in test suites
2020-06-04 Luke Kenneth Casso... add ShiftRot test case (works only because CRs are...
2020-06-04 Luke Kenneth Casso... add both logical and ALU test core
2020-06-04 Luke Kenneth Casso... whoops, docstring indentation
2020-06-04 Luke Kenneth Casso... add docstrings for read/write port connection
2020-06-04 Luke Kenneth Casso... move core code into separate functions, for clarity
2020-06-04 Luke Kenneth Casso... oops forgot to switch write-enable off
2020-06-04 Luke Kenneth Casso... comment clarify on core
2020-06-04 Luke Kenneth Casso... initialise XER from simulation
2020-06-04 Luke Kenneth Casso... messing with valid/busy signals in core test
2020-06-04 Luke Kenneth Casso... hmmm sync-delay wport write and wen
2020-06-04 Luke Kenneth Casso... test actual reg values being produced in core test
2020-06-04 Luke Kenneth Casso... move reg setup to earlier in test
2020-06-04 Luke Kenneth Casso... comment out wrflag as it should already be in the fu...
2020-06-04 Luke Kenneth Casso... test against Logical (hard-coded change)
2020-06-04 Luke Kenneth Casso... add first cut at test core
2020-06-04 Luke Kenneth Casso... sync onto fu.go_wr_i otherwise a loop occurs
2020-06-04 Luke Kenneth Casso... add rdmask and issue/busy setting
2020-06-04 Luke Kenneth Casso... connect up write-ports from Regfiles to FUs
2020-06-04 Luke Kenneth Casso... update docstring on simple/core.py
2020-06-04 Luke Kenneth Casso... move regfile/spec organiser to separate function
2020-06-04 Luke Kenneth Casso... collate fu-enable signals
2020-06-04 Luke Kenneth Casso... connect up Function Unit operand subsets
2020-06-03 Luke Kenneth Casso... forgot to add in rdflag enable
2020-06-03 Luke Kenneth Casso... whoops, regfiles are uppercase
2020-06-03 Luke Kenneth Casso... whoops needed a bit of a reorg of the data structure...
2020-06-03 Luke Kenneth Casso... hmmm got naming wrong in regfile-fu connectivity
2020-06-03 Luke Kenneth Casso... whoops names of regfiles are lower-case
2020-06-03 Luke Kenneth Casso... munge/redirect the regfile port based on the naming
2020-06-03 Luke Kenneth Casso... connect read-enable and src_i to regfile ports
2020-06-03 Luke Kenneth Casso... link up PriorityPickers on read channels
2020-06-03 Luke Kenneth Casso... put rdspecs into a different dictionary
2020-06-03 Luke Kenneth Casso... start putting a non-production core together,
2020-06-03 Luke Kenneth Casso... add a simple core, not intended for production use