2021-03-09 |
Cesar Strauss | Add some extra debug traces to the GTKWave document |
tree | commitdiff |
2021-03-09 |
Cesar Strauss | Create a new signal for the Simulator to wait on |
tree | commitdiff |
2021-03-08 |
Luke Kenneth Casso... | actually make it possible to disable svp64 on commandli... |
tree | commitdiff |
2021-03-08 |
Luke Kenneth Casso... | add option in TestRunner to disable svp64 via commandli... |
tree | commitdiff |
2021-03-08 |
Cesar Strauss | Remove the unused internal insn_done signal |
tree | commitdiff |
2021-03-08 |
Cesar Strauss | Fix argument order to match function declaration |
tree | commitdiff |
2021-03-07 |
Cesar Strauss | Merge WAIT_RESET into INSN_FETCH on the Issue FSM |
tree | commitdiff |
2021-03-07 |
Luke Kenneth Casso... | move DMI stuff to separate function in issuer.py |
tree | commitdiff |
2021-03-07 |
Luke Kenneth Casso... | update comments in issuer.py |
tree | commitdiff |
2021-03-07 |
Cesar Strauss | Implement the VL==0 loop |
tree | commitdiff |
2021-03-06 |
Cesar Strauss | Allow updating the PC and SVSTATE registers while stopped |
tree | commitdiff |
2021-03-06 |
Cesar Strauss | Begin to implement the Simple-V loop |
tree | commitdiff |
2021-03-06 |
Cesar Strauss | Do not reset pc_changed and sv_changed at instruction end |
tree | commitdiff |
2021-03-06 |
Cesar Strauss | Make the raw opcode input port of the decoder stay... |
tree | commitdiff |
2021-03-05 |
Luke Kenneth Casso... | litex expects wishbone "err" signals even if not used |
tree | commitdiff |
2021-03-05 |
Cesar Strauss | Move writing of the PC state register to the issue FSM |
tree | commitdiff |
2021-03-05 |
Cesar Strauss | Move the wait on "core stop" out of fetch, and into... |
tree | commitdiff |
2021-03-03 |
Luke Kenneth Casso... | cur_state is a global, does not have to be passed as... |
tree | commitdiff |
2021-03-03 |
Luke Kenneth Casso... | set SVSTATE in TestRunner using new TestIssuer.svstate_i |
tree | commitdiff |
2021-03-03 |
Luke Kenneth Casso... | add svstate_i to TestIssuer which mirrors pc_i |
tree | commitdiff |
2021-03-02 |
Luke Kenneth Casso... | sort out SPR setting in MMU |
tree | commitdiff |
2021-02-27 |
Cesar Strauss | Add traces for the new FSM |
tree | commitdiff |
2021-02-26 |
Luke Kenneth Casso... | remove sv_changed input to fetch_fsm, add it to issue_f... |
tree | commitdiff |
2021-02-26 |
Luke Kenneth Casso... | moving new_svstate and update_svstate into issue FSM... |
tree | commitdiff |
2021-02-26 |
Luke Kenneth Casso... | move fetch_insn_o into issue_fsm TestIssuer |
tree | commitdiff |
2021-02-26 |
Luke Kenneth Casso... | add comments, missing that VL loop ends after execution... |
tree | commitdiff |
2021-02-26 |
Cesar Strauss | Implement a decode/issue FSM between fetch and execute |
tree | commitdiff |
2021-02-24 |
Tobias Platen | test_runner.py: add needed imports |
tree | commitdiff |
2021-02-23 |
Tobias Platen | deduplicate |
tree | commitdiff |
2021-02-23 |
Luke Kenneth Casso... | add note that SVSTATE has changed, this will allow... |
tree | commitdiff |
2021-02-22 |
Luke Kenneth Casso... | move setting of NIA into fetch FSM in TestIssuer |
tree | commitdiff |
2021-02-22 |
Luke Kenneth Casso... | whoops |
tree | commitdiff |
2021-02-22 |
Luke Kenneth Casso... | moving PC-setting (NIA) out of execute_fsm in TestIssuer |
tree | commitdiff |
2021-02-22 |
Luke Kenneth Casso... | rename inter-FSM handshake signals in TestIssuer |
tree | commitdiff |
2021-02-21 |
Luke Kenneth Casso... | err trying to put in some FSM handshake signals, gettin... |
tree | commitdiff |
2021-02-21 |
Luke Kenneth Casso... | comment for where SVSTATE FSM should go |
tree | commitdiff |
2021-02-21 |
Cesar Strauss | Hide the register augmentation traces by default |
tree | commitdiff |
2021-02-21 |
Luke Kenneth Casso... | move execute_fsm to separate function in TestIssuer |
tree | commitdiff |
2021-02-21 |
Luke Kenneth Casso... | move fetch_fsm to separate function in TestIssuer |
tree | commitdiff |
2021-02-21 |
Luke Kenneth Casso... | add JTAG enable/disable of 4k SRAMs |
tree | commitdiff |
2021-02-20 |
Luke Kenneth Casso... | add QTY 4of 4k SRAMs SPBlock512W64B8W to TestIssuer... |
tree | commitdiff |
2021-02-20 |
Luke Kenneth Casso... | add option for QTY 4x 4k SRAM blocks (not added yet... |
tree | commitdiff |
2021-02-20 |
Luke Kenneth Casso... | whoops set ROM to none by mistake |
tree | commitdiff |
2021-02-20 |
Luke Kenneth Casso... | whoops spelling error |
tree | commitdiff |
2021-02-20 |
Luke Kenneth Casso... | add (unused) code for writing out SVSTATE in TestIssuer |
tree | commitdiff |
2021-02-20 |
Luke Kenneth Casso... | remove massive code-duplication, move simple "self... |
tree | commitdiff |
2021-02-20 |
Tobias Platen | add rom debugger |
tree | commitdiff |
2021-02-20 |
Tobias Platen | add mmu rom testcase |
tree | commitdiff |
2021-02-17 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2021-02-17 |
Tobias Platen | add wishbone signals to gtkwave output |
tree | commitdiff |
2021-02-17 |
Cesar Strauss | Add the SVSTATE traces to GTKWave to allow debugging... |
tree | commitdiff |
2021-02-17 |
Cesar Strauss | Initialize the core SVSTATE from the corresponding... |
tree | commitdiff |
2021-02-17 |
Cesar Strauss | Revert "Setup SVSTATE, from the test settings, at the... |
tree | commitdiff |
2021-02-17 |
Cesar Strauss | Add traces to debug SVP64 prefix decoding issues |
tree | commitdiff |
2021-02-17 |
Cesar Strauss | Setup SVSTATE, from the test settings, at the start |
tree | commitdiff |
2021-02-16 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2021-02-15 |
Tobias Platen | test case for MMU SPRs: PID and PRTBL |
tree | commitdiff |
2021-02-15 |
Cesar Strauss | Simplify obtaining the PC from the register file |
tree | commitdiff |
2021-02-15 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2021-02-14 |
Cesar Strauss | Show traces for the register numbers of the current... |
tree | commitdiff |
2021-02-14 |
Cesar Strauss | Remove obsolete comment |
tree | commitdiff |
2021-02-14 |
Luke Kenneth Casso... | add comments to TestIssuer |
tree | commitdiff |
2021-02-14 |
Luke Kenneth Casso... | add TestRunner comments |
tree | commitdiff |
2021-02-14 |
Luke Kenneth Casso... | add SVSTATE reading to TestIssuer |
tree | commitdiff |
2021-02-14 |
Luke Kenneth Casso... | add extra FSM explanatory comments to TestIssuer |
tree | commitdiff |
2021-02-13 |
Luke Kenneth Casso... | use function for getting instruction from 32/64 bit... |
tree | commitdiff |
2021-02-13 |
Cesar Strauss | Fetch and decode the SVP64 prefix |
tree | commitdiff |
2021-02-13 |
Cesar Strauss | Check the PC value at the end of each instruction |
tree | commitdiff |
2021-02-13 |
Luke Kenneth Casso... | add SVP64 TestIssuer separate unit test |
tree | commitdiff |
2021-02-13 |
Luke Kenneth Casso... | split out TestRunner into separate module |
tree | commitdiff |
2021-02-12 |
Luke Kenneth Casso... | add SVSTATE to TestCase infrastructure for use in TestI... |
tree | commitdiff |
2021-02-11 |
Luke Kenneth Casso... | comments in TestIssuer for SVP64PrefixDecoder |
tree | commitdiff |
2021-02-06 |
Cesar Strauss | Fix whitespace |
tree | commitdiff |
2021-02-06 |
Cesar Strauss | Extract the fetch FSM out from the main FSM |
tree | commitdiff |
2021-02-04 |
Tobias Platen | src/soc/fu/mmu/fsm.py: add debug outputs for gtkwave |
tree | commitdiff |
2021-02-04 |
Tobias Platen | pass SPR MicroOp to MMU function unit |
tree | commitdiff |
2021-02-01 |
Tobias Platen | extending the GTKWave document in test_issuer when... |
tree | commitdiff |
2021-02-01 |
Cesar Strauss | Add GTKWave document to test_issuer |
tree | commitdiff |
2021-01-18 |
Tobias Platen | uncomment #FIXME in unit_test |
tree | commitdiff |
2021-01-16 |
Tobias Platen | move microwatt_mmu bool variable to pspec |
tree | commitdiff |
2021-01-15 |
Tobias Platen | add microwatt_mmu boolean variable to core and compunits |
tree | commitdiff |
2021-01-08 |
Tobias Platen | fix broken testcase for simple core |
tree | commitdiff |
2020-11-13 |
Luke Kenneth Casso... | reduce clkcsel ls180 width (2 pins), rename pll_18... |
tree | commitdiff |
2020-11-13 |
Luke Kenneth Casso... | rename and add pll lock signal to ls180 |
tree | commitdiff |
2020-11-13 |
Luke Kenneth Casso... | add enable/disable arguments (not ideal but it works... |
tree | commitdiff |
2020-11-10 |
Luke Kenneth Casso... | remove ClockSelect module, use DummyPLL |
tree | commitdiff |
2020-10-22 |
Luke Kenneth Casso... | add query about cross-domain on the JTAG enable of WB |
tree | commitdiff |
2020-10-22 |
Luke Kenneth Casso... | add JTAG enable/disable of wishbone to TestIssuer |
tree | commitdiff |
2020-10-21 |
Cole Poirier | versa_ecp5 adds ability to build and load for ulx3s85f... |
tree | commitdiff |
2020-10-16 |
Luke Kenneth Casso... | re-enable tests |
tree | commitdiff |
2020-10-16 |
Luke Kenneth Casso... | manually run coresync clock for test issuer |
tree | commitdiff |
2020-10-16 |
Luke Kenneth Casso... | set defaults in pspec |
tree | commitdiff |
2020-10-15 |
Luke Kenneth Casso... | wrong pspec variable in selecting pll clock |
tree | commitdiff |
2020-10-15 |
Luke Kenneth Casso... | sorting out missing clock somewhere |
tree | commitdiff |
2020-10-15 |
Luke Kenneth Casso... | use "enable" and set default actions in getopt |
tree | commitdiff |
2020-10-14 |
Cole Poirier | issuer_verilog.py update to use commandline args using... |
tree | commitdiff |
2020-10-11 |
Luke Kenneth Casso... | add way to bypass PLL for ECP5 and sim |
tree | commitdiff |
2020-10-11 |
Luke Kenneth Casso... | comment out XICS/GPIO interrupt test, causes ECP5 litex... |
tree | commitdiff |
2020-10-11 |
Luke Kenneth Casso... | litex sim.py operational |
tree | commitdiff |
2020-10-07 |
Luke Kenneth Casso... | reorder / reorganise reset signals slightly |
tree | commitdiff |
next |