2021-12-27 |
Cesar Strauss | Fix indentation |
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2021-12-26 |
Luke Kenneth... | good grief, finally tracked down a piece of missing... |
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2021-12-26 |
Luke Kenneth... | whoops, using variable RegStage0 in dcache stage_0... |
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2021-12-26 |
Luke Kenneth... | missed reset of d_valid in dcache.py and missed that its |
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2021-12-26 |
Luke Kenneth... | rename addr to raddr in LoadStore1 to avoid conflict... |
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2021-12-25 |
Luke Kenneth... | add mmu.bin test2 to much simpler test_loadstore1.py |
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2021-12-25 |
Luke Kenneth... | move msr in test_loadstore1.py outside of conditional... |
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2021-12-25 |
Luke Kenneth... | whitespace |
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2021-12-25 |
Luke Kenneth... | move microwatt mmu.bin test 3 page table to test pageta... |
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2021-12-25 |
Luke Kenneth... | wait for MMU "done" when setting PRTBL and PIDR |
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2021-12-25 |
Luke Kenneth... | add microwatt mmu.bin regression test test_mmu_3 |
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2021-12-24 |
Luke Kenneth... | enable instruction redirect in mmu ifetch test |
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2021-12-23 |
Luke Kenneth... | somehow managed to miss out setting r1.forward_valid1... |
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2021-12-23 |
Luke Kenneth... | uniquify names in dcache.py |
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2021-12-23 |
Luke Kenneth... | allow MSR reset to default to a value set by issuer_ver... |
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2021-12-23 |
Luke Kenneth... | pass in msr_reset to issuer_verilog.py |
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2021-12-23 |
Luke Kenneth... | add ability to set the reset values of RegFileArray |
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2021-12-23 |
Cesar Strauss | Remove extra wait on core_stop_o at end of Execute. |
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2021-12-23 |
Cesar Strauss | Re-enable core stopped signal when stopped. |
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2021-12-22 |
Luke Kenneth... | only use a single variable for ack adjusting in dcache.py |
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2021-12-22 |
Luke Kenneth... | fix issues with running core in DMI "stopped" status... |
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2021-12-22 |
Luke Kenneth... | when setting DSISR in LoadStore1 use correct load bit... |
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2021-12-22 |
Luke Kenneth... | use correct X-Form L field in OP_MTMSRD |
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2021-12-22 |
Luke Kenneth... | check problem state in OP_MTMSRD from original reg... |
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2021-12-22 |
Luke Kenneth... | whoops, use MSR.IR for I-Cache fetch! |
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2021-12-22 |
Luke Kenneth... | remove unneeded state in LoadStore1 |
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2021-12-22 |
Luke Kenneth... | clear instruction fault on exception WAIT_MMU ACK in... |
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2021-12-22 |
Luke Kenneth... | clear out instr_fault when exception is thrown |
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2021-12-22 |
Luke Kenneth... | clear instruction fault on idle/valid in Loadstore1 |
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2021-12-22 |
Luke Kenneth... | ooo far too late at night to be doing this |
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2021-12-22 |
Luke Kenneth... | whoops use C not Const |
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2021-12-22 |
Luke Kenneth... | whoops use C not Const |
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2021-12-22 |
Luke Kenneth... | remove bus_ack (found bug in Simulation, sorted) |
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2021-12-22 |
Luke Kenneth... | bug in mmu setting radix tree size with one extra bit |
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2021-12-21 |
Luke Kenneth... | continue to assert PC in FetchFSM if needed |
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2021-12-21 |
Luke Kenneth... | enable I-Cache wishbone memory type in issuer_verilog... |
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2021-12-21 |
Luke Kenneth... | whoops issuer_verilog.py enabling mmu has to pass micro... |
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2021-12-21 |
Luke Kenneth... | for each unit test case in test_issuer_mmu_data_path... |
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2021-12-21 |
Luke Kenneth... | test_issuer_mmu_data_path.py needs to use wb_get because of |
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2021-12-21 |
Luke Kenneth... | mmu code-comments |
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2021-12-21 |
Luke Kenneth... | comments |
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2021-12-21 |
Luke Kenneth... | use prtbl in proc_tbl_wait in mmu |
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2021-12-21 |
Luke Kenneth... | mmu.py comments |
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2021-12-20 |
Luke Kenneth... | set up DAR correctly in unit tests, added set_ldst_spr... |
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2021-12-20 |
Luke Kenneth... | unit tests for SPRs when MMU enabled, |
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2021-12-20 |
Luke Kenneth... | more code-comments |
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2021-12-20 |
Luke Kenneth... | code-comments in MMU |
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2021-12-20 |
Luke Kenneth... | prefer not to invert when doing if/else. |
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2021-12-20 |
Luke Kenneth... | more code-comments |
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2021-12-20 |
Luke Kenneth... | add RTPDE - Radit Tree Page Directory Entry - Record... |
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2021-12-20 |
Luke Kenneth... | add (and ues) PRTBL Record in MMU |
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2021-12-20 |
Luke Kenneth... | create PGTBL Record and use it in MMU page_table_idle |
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2021-12-19 |
Luke Kenneth... | add hard stop address in ifetch unit test, bit of a... |
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2021-12-19 |
Luke Kenneth... | set terminate if core terminate requested |
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2021-12-19 |
Luke Kenneth... | code-comments |
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2021-12-19 |
Luke Kenneth... | add DMI STOPADDR register and use it in HDLRunner to... |
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2021-12-19 |
Luke Kenneth... | break out when core is stopped in HDLRunner |
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2021-12-18 |
Luke Kenneth... | add link to XICS bugreport |
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2021-12-18 |
Luke Kenneth... | sort out reset signalling after tracking down Simulatio... |
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2021-12-18 |
Luke Kenneth... | add icache/dcache/mmu unit test for TestIssuer |
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2021-12-18 |
Luke Kenneth... | get instructions to re-run in issuer after I-Cache... |
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2021-12-18 |
Luke Kenneth... | forgot to connect up I-Cache to MMU |
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2021-12-18 |
Luke Kenneth... | move connection of bus.stall in icache.py, |
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2021-12-18 |
Luke Kenneth... | tidyup |
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2021-12-18 |
Luke Kenneth... | tlb_req_index is TLB_BITS long not TLB_SIZE |
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2021-12-16 |
Luke Kenneth... | whoops, a Simulation bug, dcache bus ack Signal needed... |
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2021-12-16 |
Luke Kenneth... | give names to MMU records |
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2021-12-16 |
Luke Kenneth... | set_mmu_spr was using the slow-SPR index for the regfile |
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2021-12-16 |
Luke Kenneth... | whoops remove duplicate code (cut/paste error) no harm... |
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2021-12-15 |
Luke Kenneth... | remove more unneeded code |
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2021-12-15 |
Luke Kenneth... | read MSR.PR and MSR.DR and update ICache priv/virt... |
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2021-12-15 |
Luke Kenneth... | remove more of SVP64 from TestIssuerInternalInOrder |
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2021-12-15 |
Luke Kenneth... | remove update of pc, msr and svstate from TestIssuerInOrder |
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2021-12-15 |
Luke Kenneth... | move update of pc, msr and svstate into TestIssuerBase |
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2021-12-15 |
Luke Kenneth... | comment-out TestIssuerInternalInorder for now |
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2021-12-15 |
Luke Kenneth... | move alternative TestIssuerInternalInOrder to new file |
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2021-12-15 |
Luke Kenneth... | split out common elaboratable code from TestIssuer, |
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2021-12-15 |
Luke Kenneth... | big split-out of common functions in TestIssuer to... |
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2021-12-15 |
Luke Kenneth... | simplifying / tidyup of TestIssuer to get CoreState |
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2021-12-15 |
Luke Kenneth... | sort out MSR, read/write in same way as PC/SVSTATE... |
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2021-12-15 |
Luke Kenneth... | whoops accidentally commented out setup of instructions |
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2021-12-15 |
Luke Kenneth... | get fetch_failed working with no MMU |
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2021-12-14 |
Tobias Platen | test_loadstore1.py: test_loadstore1_ifetch_multi now... |
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2021-12-14 |
Luke Kenneth... | trying to get TestIssuer FSM to respond correctly to... |
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2021-12-14 |
Luke Kenneth... | get OP_FETCH_FAILED to respond/return an exception... |
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2021-12-14 |
Luke Kenneth... | update wb_get memory with instructions if required |
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2021-12-14 |
Tobias Platen | fix test_loadstore1_ifetch_multi() in test_loadstore1.py |
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2021-12-14 |
Tobias Platen | wip test case for virtual address fetch using fetch... |
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2021-12-14 |
Tobias Platen | fix test_loadstore1_ifetch_multi() |
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2021-12-14 |
Jonathan Neuschäfer | GitLab-CI: Increase clone depth |
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2021-12-14 |
Luke Kenneth... | MMU LOOKUP for fetch failed, priv mode is inversion... |
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2021-12-14 |
Luke Kenneth... | link MSR.PR into MMU FSM OP_FETCH_FAILED |
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2021-12-13 |
Luke Kenneth... | return temporarily to older version of pinmux submodule |
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2021-12-13 |
Luke Kenneth... | request a flush of icache to clear the instruction... |
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2021-12-13 |
Tobias Platen | try to get multi test running |
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2021-12-13 |
Tobias Platen | comments about test_loadstore1_ifetch() |
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2021-12-13 |
Luke Kenneth... | fix test_loadstore1.py with MSR=PR/DR |
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2021-12-13 |
Luke Kenneth... | set pr=0 because privileged mode is pr=0 not pr=1 |
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2021-12-13 |
Luke Kenneth... | add in missing MSRSpec import |
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2021-12-13 |
Luke Kenneth... | commented-out code |
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