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correct default to zero string not zero int
[soc.git] / src / soc / bus /
2022-04-03 Luke Kenneth Casso... fix some of instantiation errors in opencores_ethmac.py tree | commitdiff
2022-04-02 Raptor Engineering... Fix opencores EthMAC module wiring tree | commitdiff
2022-03-31 Luke Kenneth Casso... invert cs_n pin in Tercel tree | commitdiff
2022-03-30 Luke Kenneth Casso... nope, default features in Tercel WB Buses need to not... tree | commitdiff
2022-03-29 Luke Kenneth Casso... add bus.err to list of default Wishbone signals in... tree | commitdiff
2022-03-29 Luke Kenneth Casso... byte-reverse Tercel read/write data and config bus... tree | commitdiff
2022-03-29 Luke Kenneth Casso... set clock freq Constant length to 32-bit in Tercel. tree | commitdiff
2022-03-29 Luke Kenneth Casso... self.specials does not exist, Instances must be added... tree | commitdiff
2022-03-29 Luke Kenneth Casso... more sorting out wishbone names in Tercel tree | commitdiff
2022-03-29 Luke Kenneth Casso... fix names of Instance signals in Tercel tree | commitdiff
2022-03-29 Luke Kenneth Casso... sort out variable names in Tercel tree | commitdiff
2022-03-29 Luke Kenneth Casso... self.comb does not exist, comb is a local temp-var... tree | commitdiff
2022-03-29 Luke Kenneth Casso... whitespace cleanup (80 char limit) tree | commitdiff
2022-03-29 Raptor Engineering... Add initial integration for OpenCores 10/100 Ethernet MAC tree | commitdiff
2022-03-18 Luke Kenneth Casso... whitespace cleanup (80 char limit, pep8) tree | commitdiff
2022-03-16 Raptor Engineering... Add initial Tercel integration tree | commitdiff
2022-03-08 Luke Kenneth Casso... work-in-progress on sdram opencores wrapper tree | commitdiff
2022-02-18 Luke Kenneth Casso... add SDRAM Configuration Record tree | commitdiff
2022-02-18 Luke Kenneth Casso... parameterise I-Cache similar to D-Cache. lots of "self." tree | commitdiff
2022-02-17 Luke Kenneth Casso... add opencores SDRAM verilog wrapper tree | commitdiff
2022-02-16 Luke Kenneth Casso... connect UART16550 pins if given tree | commitdiff
2022-02-15 Luke Kenneth Casso... for *write* the counter-address on downconvert was... tree | commitdiff
2022-02-15 Luke Kenneth Casso... add wishbone downconvert "skip" of slave sel so that... tree | commitdiff
2022-02-15 Luke Kenneth Casso... add SysCon reg_info, has uart and has large SYSCON tree | commitdiff
2022-02-15 Luke Kenneth Casso... sigh, stall was not working but actually turns out... tree | commitdiff
2022-02-15 Luke Kenneth Casso... add option to specify UART16550 width (32/8) tree | commitdiff
2022-02-15 Luke Kenneth Casso... add beginnings of syscon bus peripheral tree | commitdiff
2022-02-15 Luke Kenneth Casso... update comments tree | commitdiff
2022-02-15 Luke Kenneth Casso... resolve WBDownConvert ack issues when stall is active tree | commitdiff
2022-02-14 Luke Kenneth Casso... strip first 3 bits of WB address from microwatt d/i... tree | commitdiff
2022-02-14 Luke Kenneth Casso... slave sends stall signal, master receives, in tree | commitdiff
2022-02-14 Luke Kenneth Casso... sort out ExternalCore signal names tree | commitdiff
2022-02-14 Luke Kenneth Casso... add wishbone slave signal to downconvert if present tree | commitdiff
2022-02-14 Luke Kenneth Casso... add external core verilog wrapper, ironically around... tree | commitdiff
2022-02-13 Luke Kenneth Casso... bugfixing for ls2 imports of uart16550 tree | commitdiff
2022-02-09 Luke Kenneth Casso... add opencores uart16550 instance wrapper tree | commitdiff
2021-05-27 Luke Kenneth Casso... corrections on spblock ack tree | commitdiff
2021-05-27 Luke Kenneth Casso... classic wishbone mode: must not do ack if already acked tree | commitdiff
2021-05-24 Luke Kenneth Casso... whoops sort out name of SPBlock RAM tree | commitdiff
2021-05-02 Luke Kenneth Casso... quick hack to SRAM test and to dcache to enable classic... tree | commitdiff
2021-04-30 Luke Kenneth Casso... sort out spblock 4k sram cell instance name to match... tree | commitdiff
2021-04-26 Luke Kenneth Casso... comment read ack in sram tree | commitdiff
2021-04-20 Luke Kenneth Casso... use soc.bus.sram instead of nmigen_soc.wishbone.sram tree | commitdiff
2021-04-20 Luke Kenneth Casso... add wishbone sram.py (move from nmigen-soc) tree | commitdiff
2021-04-19 Luke Kenneth Casso... give independent names to spblock512w64b8ws tree | commitdiff
2021-04-18 Luke Kenneth Casso... give spblock512 a name as a submodule tree | commitdiff
2021-04-18 Luke Kenneth Casso... rename SPBlock_512W64B8W to lowercase tree | commitdiff
2021-04-06 Luke Kenneth Casso... 4k SRAM Instance needs write-enable @ 8-bit width tree | commitdiff
2021-03-06 Luke Kenneth Casso... remove blackbox attribute on SPBlock_512W64B8W tree | commitdiff
2021-03-05 Luke Kenneth Casso... extend name of sram4k block with _wb suffix tree | commitdiff
2021-02-21 Luke Kenneth Casso... add JTAG enable/disable of 4k SRAMs tree | commitdiff
2021-02-20 Luke Kenneth Casso... add black-box attribute to 4k SRAM cell tree | commitdiff
2021-02-20 Luke Kenneth Casso... add QTY 4of 4k SRAMs SPBlock512W64B8W to TestIssuer... tree | commitdiff
2021-02-20 Luke Kenneth Casso... add Wishbone-wrapped SPBlock_512W64B8W tree | commitdiff
2020-12-20 Cesar StraussAdd support for CXXSim simulation tree | commitdiff
2020-09-05 Luke Kenneth Casso... add simple GPIO wishbone bus to litex sim.py tree | commitdiff
2020-09-05 Luke Kenneth Casso... move wb read/write to separate util test library and... tree | commitdiff
2020-09-05 Luke Kenneth Casso... add simple wishbone GPIO peripheral tree | commitdiff
2020-08-21 Luke Kenneth Casso... ld/st bus reduction test operational tree | commitdiff
2020-08-21 Luke Kenneth Casso... first test of down-converted load/store from 64 to... tree | commitdiff
2020-08-21 Luke Kenneth Casso... first test of down-converted load/store from 64 to... tree | commitdiff
2020-08-21 Luke Kenneth Casso... add in WishboneDownConvert into LoadStoreUnitInterface tree | commitdiff
2020-08-21 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc tree | commitdiff
2020-08-20 Luke Kenneth Casso... bugfix wishbone downconvert using wb sram 64-to-32... tree | commitdiff
2020-08-20 Luke Kenneth Casso... add a wishbone upconverter tree | commitdiff
2020-07-29 Jacob Lifshayadd __init__.py to all source directories tree | commitdiff
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master' tree | commitdiff
2020-07-22 Jacob Lifshayformat code tree | commitdiff
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org... tree | commitdiff
2020-07-07 Luke Kenneth Casso... whoops error in test of dynamic parameter tree | commitdiff
2020-07-07 Luke Kenneth Casso... sort-of got binary execution test working tree | commitdiff
2020-07-07 Luke Kenneth Casso... code-shuffle on testing to prepare loading large files... tree | commitdiff
2020-07-01 Luke Kenneth Casso... minor reorg on how Bus and Config classes are set up tree | commitdiff
2020-06-29 Luke Kenneth Casso... fetch instructions from bare wishbone fetch unit tree | commitdiff
2020-06-28 Luke Kenneth Casso... read from instruction memory using FetchUnitInterface tree | commitdiff
2020-06-28 Luke Kenneth Casso... sram address do not cut by LSBs tree | commitdiff
2020-06-27 Luke Kenneth Casso... make Memory accessible via TestSRAMBareLoadStoreUnit tree | commitdiff
2020-06-26 Luke Kenneth Casso... investigating why write-enable not getting passed through tree | commitdiff
2020-06-26 Luke Kenneth Casso... whoops forgot to call parent elaborate tree | commitdiff
2020-06-26 Luke Kenneth Casso... add test of SRAM through wishbone bus tree | commitdiff
2020-06-26 Luke Kenneth Casso... code-morph which redirects lsmem unit test through... tree | commitdiff
2020-06-26 Luke Kenneth Casso... add a test SRAM that lives behind a minerva LoadStoreUn... tree | commitdiff
2020-06-20 Luke Kenneth Casso... expand Memory width to 64 and granularity to 16 in... tree | commitdiff
2020-06-20 Luke Kenneth Casso... add asserts to check data output is correct tree | commitdiff
2020-06-20 Luke Kenneth Casso... add test_sram_wishbone.py tree | commitdiff