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MMU: get store to activate only when data is available, and to wait till done
[soc.git]
/
src
/
soc
/
fu
/
mmu
/
fsm.py
2021-05-03
Luke Kenneth Casso...
MMU: get store to activate only when data is available...
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2021-05-03
Luke Kenneth Casso...
disable the cache for now, whilst testing read/write...
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2021-05-02
Luke Kenneth Casso...
use Const to define bit-length when comparing top nibbl...
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2021-05-02
Luke Kenneth Casso...
mmu FSM store in dcache: only put data onto d_in on...
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2021-05-02
Luke Kenneth Casso...
return d_out.valid instead of always "ok" in MMU FSM
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2021-05-02
Luke Kenneth Casso...
HACK WARNING: disable d-cache on hard-coded address...
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2021-05-01
Luke Kenneth Casso...
store data in microwatt dcache goes in one cycle AFTER...
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2021-05-01
Luke Kenneth Casso...
only do dcache lookup for now
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2021-04-30
Luke Kenneth Casso...
comments on dcache-to-mmu link
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2021-04-30
Luke Kenneth Casso...
add a TestSRAM variant of LoadStore1, for being able...
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2021-04-30
Luke Kenneth Casso...
hook up dcache wb_in/out to PortInterfaceBase Wishbone...
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2021-04-30
Luke Kenneth Casso...
set up LoadStore1 in ConfigMemoryPortInterface and...
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2021-04-29
Luke Kenneth Casso...
comment out adding mmu and dcache to pspec in MMU FSM
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2021-04-29
Luke Kenneth Casso...
move dcache into Loadstore1
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2021-04-27
Luke Kenneth Casso...
return read data out from Loadstore1 only when valid
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2021-04-26
Luke Kenneth Casso...
hook up MSR into MMU (TODO, use a lot less bits)
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2021-04-23
Luke Kenneth Casso...
move over to from openpower imports
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2021-03-30
Alain D D Williams
Merge branch 'master' of git.libre-soc.org:soc
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2021-03-28
Luke Kenneth Casso...
rather invasive reduction of SPR regfile size
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2021-03-02
Luke Kenneth Casso...
operating correctly, not directing MMU SPRs to SPR...
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2021-03-02
Luke Kenneth Casso...
must always set ok for writing out data otherwise it...
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2021-02-18
Tobias Platen
mmu: remove TestMemory
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2021-02-16
Tobias Platen
mmureq handling
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2021-02-16
Tobias Platen
dcache error handling
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2021-02-05
Tobias Platen
fix hanging simulation
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2021-02-04
Tobias Platen
src/soc/fu/mmu/fsm.py: add debug outputs for gtkwave
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2021-01-19
Tobias Platen
connect LDSTException to MMU and DCache
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2021-01-19
Tobias Platen
connect wishbone bus to test memory
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2021-01-18
Tobias Platen
fu/mmu/fsm.py: connect valid and load signals
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2021-01-17
Tobias Platen
add test memory for simulation
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2021-01-16
Tobias Platen
clean up test case for tlbie and dcbz
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2021-01-06
Tobias Platen
fu/mmu/fsm.py: mfspr!=mtspr
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2020-11-16
Tobias Platen
add class LoadStore1(PortInterfaceBase)
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2020-11-07
Tobias Platen
fixed a bug in src/soc/fu/mmu/fsm.py
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2020-10-08
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-10-08
Luke Kenneth Casso...
add incoming PortInterface to be connected to LoadStore...
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2020-09-15
Luke Kenneth Casso...
instantiate MMU from AllFunctionUnits
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2020-09-15
Luke Kenneth Casso...
add edge-triggering to dcache/mmu "valid"
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2020-09-15
Luke Kenneth Casso...
add OP_MFSPR to mmu
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2020-09-15
Luke Kenneth Casso...
use convenience vars
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2020-09-15
Luke Kenneth Casso...
add OP_TLBIE to mmu fsm
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2020-09-15
Luke Kenneth Casso...
add OP_DCBZ to mmu fsm, needs RA to be added to MMU...
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2020-09-15
Luke Kenneth Casso...
add MMU MTSPR connection into FSM
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2020-09-15
Luke Kenneth Casso...
add in MMU and DCache into MMU FSM
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2020-09-15
Luke Kenneth Casso...
add mmu fsm
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