disable cxxsim for now
[soc.git] / src /
2020-07-21 Luke Kenneth Casso... disable cxxsim for now
2020-07-21 Luke Kenneth Casso... move cia and msr to trap input record
2020-07-21 Luke Kenneth Casso... set ISACaller.msr rather than namespace[MSR]
2020-07-21 Luke Kenneth Casso... when running an exception (trap) after "reset" must...
2020-07-21 Luke Kenneth Casso... spurious imports of FHDLTestCase, should be from nmutil
2020-07-21 Luke Kenneth Casso... whitespace
2020-07-21 Luke Kenneth Casso... add PC (CIA) to PowerDecode2 "state" for passing into...
2020-07-21 Luke Kenneth Casso... add msr exception bits setting function in hardware
2020-07-21 Luke Kenneth Casso... make cxxsim optional and print warning
2020-07-21 Luke Kenneth Casso... corrections to trap proof see
2020-07-21 Luke Kenneth Casso... use alias for msr_i in trap proof
2020-07-21 Luke Kenneth Casso... correct trap spec page interrupt ref
2020-07-20 Samuel A. Falvo IIRework SC properties to conform to style
2020-07-20 Samuel A. Falvo IIFormal properties for RFID.
2020-07-20 Cesar StraussDocument the move of sdir from data_i to op.
2020-07-20 Cesar StraussRemove extra yield from test case.
2020-07-19 Luke Kenneth Casso... do not start core in terminated mode
2020-07-19 Luke Kenneth Casso... explicitly set up a pc_i_ok signal in test_microwatt.py
2020-07-19 Luke Kenneth Casso... expose core_stop_i to outside as well
2020-07-19 Luke Kenneth Casso... set go_insn_i to non-resetless
2020-07-19 Luke Kenneth Casso... add issuer verilog generator
2020-07-19 Luke Kenneth Casso... update to expose signals at top-level of issuer
2020-07-19 Luke Kenneth Casso... convert compalu multi test to Simulator() (was run_simu...
2020-07-19 Luke Kenneth Casso... convert compalu multi test to Simulator() (was run_simu...
2020-07-19 Luke Kenneth Casso... use same write_vcd for cxxsim as pysim
2020-07-19 Luke Kenneth Casso... fix bug in alu_fsm.py found by cxxsim: missing one...
2020-07-19 Luke Kenneth Casso... add some CompUnit demo tests of the alu_fsm example
2020-07-19 Luke Kenneth Casso... move sdir to CompFSMOpSubset in alu_fsm example
2020-07-19 Luke Kenneth Casso... add CompFSMOpSubset, also change dir to sdir
2020-07-19 Luke Kenneth Casso... remove unneeded import
2020-07-19 Luke Kenneth Casso... if nmigen.sim.pysim import fails use nmigen.back.pysim
2020-07-19 Luke Kenneth Casso... use iocontrol PrevControl / NextControl instead of...
2020-07-19 Luke Kenneth Casso... add DivTestCase to test_issuer.py (commented out for...
2020-07-19 Cesar StraussImplement control path and unit test.
2020-07-18 Luke Kenneth Casso... worked out that DivPipeSpec can be given a default...
2020-07-18 Luke Kenneth Casso... missing conversion of DIV to Div
2020-07-18 Luke Kenneth Casso... add option to generate verilog
2020-07-18 Luke Kenneth Casso... whoops use slice not range
2020-07-18 Luke Kenneth Casso... syntax error
2020-07-18 Cesar StraussImplement the Shifter data path
2020-07-18 Cesar StraussDocument move of the next port data
2020-07-18 Luke Kenneth Casso... add SR latch cxxrtl backend demo
2020-07-18 Luke Kenneth Casso... add comment and copy of pseudo-code for OP_RFID into...
2020-07-18 Luke Kenneth Casso... review of OP_RFID showed up some errors
2020-07-18 Luke Kenneth Casso... corrections to trap main_stage.py OP_RFID according...
2020-07-18 Samuel A. Falvo IIWIP: FV failing for unknown reasons.
2020-07-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-18 Jacob Lifshayadd div fsm core (`DivState*`) with tests
2020-07-18 Samuel A. Falvo IIFailing test: fast1/fast2 vs srr0/srr1? on trap pipe
2020-07-18 Samuel A. Falvo IIforgot to clean up workspace in source
2020-07-18 Samuel A. Falvo IIFV props for SC instruction
2020-07-17 Samuel A. Falvo IIFirst FV property for trap unit
2020-07-17 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-17 Jacob Lifshaystart adding FSMDivCore*
2020-07-17 Luke Kenneth Casso... comment explaining why not to call self.trap in PowerDe...
2020-07-17 Luke Kenneth Casso... likewise cut across latest Minerva loadstore with line...
2020-07-17 Luke Kenneth Casso... sigh easier to just do a line-for-line comparison of...
2020-07-17 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-17 Luke Kenneth Casso... port minerva cache fixes
2020-07-17 Luke Kenneth Casso... forward-port minerva loadstore bugfix
2020-07-17 Luke Kenneth Casso... comments
2020-07-17 Luke Kenneth Casso... whitespace
2020-07-17 Luke Kenneth Casso... use convenience vars in spr proof
2020-07-17 Samuel A. Falvo IIFlesh out SPR-related FV properties.
2020-07-17 Luke Kenneth Casso... whitespace
2020-07-17 Luke Kenneth Casso... whitespace
2020-07-17 Jacob Lifshayadd simulation-only division core using nmigen div...
2020-07-17 Jacob Lifshayrename DIV->Div to be consistent
2020-07-17 Jacob Lifshayformat div code
2020-07-17 Jacob Lifshayadd missing fixedldstcache.py to .gitignore
2020-07-16 Luke Kenneth Casso... whoops tried doing mtspr priv, it failed but failed... div_pipeline
2020-07-16 Luke Kenneth Casso... get shiftrot compunit working
2020-07-16 Luke Kenneth Casso... more tidyup on use of CompOpSubsetBase
2020-07-16 Luke Kenneth Casso... use CompOpSubsetBase in ldst record
2020-07-16 Luke Kenneth Casso... sigh, bug in sprset.patch
2020-07-16 Luke Kenneth Casso... update cr input record to use new CompOpSubsetBase
2020-07-16 Luke Kenneth Casso... add regression test on setb simulator error
2020-07-16 Luke Kenneth Casso... use CompOpSubsetBase class in Branch op record
2020-07-16 Luke Kenneth Casso... get branch compunit working (missing bigendian arg)
2020-07-16 Luke Kenneth Casso... get trap compunit test working, adding bigendian and msr
2020-07-16 Luke Kenneth Casso... add mfmsr trap tests
2020-07-15 Luke Kenneth Casso... use new CompOpSubsetBase in trap
2020-07-15 Luke Kenneth Casso... remove unneeded comment in trap msin stage
2020-07-15 Luke Kenneth Casso... remove unneeded comment in trap pipe_data
2020-07-15 Luke Kenneth Casso... document branch pipeline relationship with PowerDecode2
2020-07-15 Luke Kenneth Casso... simplify instr_is_priv
2020-07-15 Luke Kenneth Casso... move traptype to soc.consts
2020-07-15 Luke Kenneth Casso... add better comments on mul overflow
2020-07-15 Luke Kenneth Casso... test privileged rfid call
2020-07-15 Luke Kenneth Casso... spelling error
2020-07-15 Luke Kenneth Casso... range of testing overflow was incorrect in mul
2020-07-15 Luke Kenneth Casso... set MSR up properly for privileged mtmsr test
2020-07-15 Luke Kenneth Casso... whoops forgot to update PC after trap in ISACaller
2020-07-15 Luke Kenneth Casso... move priv test to above illegal/trap test
2020-07-15 Luke Kenneth Casso... comments on IntegerData class
2020-07-15 Luke Kenneth Casso... import PipeContext not FPPipeContext
2020-07-15 Luke Kenneth Casso... minor reorg on PowerDecoder2, use switch/case rather...
2020-07-15 Luke Kenneth Casso... comments on SPRmap done in PowerDecode2
2020-07-15 Luke Kenneth Casso... comments on SPRmap done in PowerDecode2
2020-07-15 Luke Kenneth Casso... use case statement in PowerDecode2
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