"""
from nmigen import Signal, Record
from nmutil.iocontrol import RecordObject
-from soc.decoder.power_enums import InternalOp, CryIn, Function, SPR, LDSTMode
+from soc.decoder.power_enums import MicrOp, CryIn, Function, SPR, LDSTMode
class Data(Record):
RecordObject.__init__(self, name=name)
- self.insn_type = Signal(InternalOp, reset_less=True)
+ self.insn_type = Signal(MicrOp, reset_less=True)
self.fn_unit = Signal(Function, reset_less=True)
self.imm_data = Data(64, name="imm")
from soc.decoder.power_enums import (In1Sel, In2Sel, In3Sel,
OutSel, RC, Form, Function,
LdstLen, CryIn,
- InternalOp, SPR, get_csv)
+ MicrOp, SPR, get_csv)
from soc.decoder.power_decoder2 import (PowerDecode2,
Decode2ToExecute1Type)
import unittest
self.comb += self.assert_dec1_signals(dec1, row)
with self.m.Default():
self.comb += Assert(dec.op.internal_op ==
- InternalOp.OP_ILLEGAL)
+ MicrOp.OP_ILLEGAL)
def handle_subdecoders(self, dec1, decoders):
def assert_dec1_signals(self, dec, row):
op = dec.op
return [Assert(op.function_unit == Function[row['unit']]),
- Assert(op.internal_op == InternalOp[row['internal op']]),
+ Assert(op.internal_op == MicrOp[row['internal op']]),
Assert(op.in1_sel == In1Sel[row['in1']]),
Assert(op.in2_sel == In2Sel[row['in2']]),
Assert(op.in3_sel == In3Sel[row['in3']]),
from soc.decoder.power_decoder import create_pdecode, PowerOp
from soc.decoder.power_enums import (In1Sel, In2Sel, In3Sel,
OutSel, RC, Form,
- InternalOp, SPR)
+ MicrOp, SPR)
from soc.decoder.power_decoder2 import (PowerDecode2,
Decode2ToExecute1Type)
import unittest
comb += Assert(pdecode2.e.read_reg1.data == ra)
comb += Assert(pdecode2.e.read_reg1.ok == 1)
op = pdecode.op.internal_op
- with m.If((op == InternalOp.OP_BC) |
- (op == InternalOp.OP_BCREG)):
+ with m.If((op == MicrOp.OP_BC) |
+ (op == MicrOp.OP_BCREG)):
with m.If(~self.instr_bits(8)):
comb += Assert(pdecode2.e.read_spr1.data == SPR.CTR)
comb += Assert(pdecode2.e.read_spr1.ok == 1)
- with m.If((op == InternalOp.OP_MFSPR) |
- (op == InternalOp.OP_MTSPR)):
+ with m.If((op == MicrOp.OP_MFSPR) |
+ (op == MicrOp.OP_MTSPR)):
comb += Assert(pdecode2.e.read_spr1.data == self.instr_bits(11, 20))
comb += Assert(pdecode2.e.read_spr1.ok == 1)
from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
selectconcat)
from soc.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
- insns, InternalOp)
+ insns, MicrOp)
from soc.decoder.helpers import exts
from soc.consts import PI, MSR
rc_ok = yield self.dec2.e.do.rc.ok
# grrrr have to special-case MUL op (see DecodeOE)
print ("ov en rc en", ov_ok, ov_en, rc_ok, rc_en, int_op)
- if int_op in [InternalOp.OP_MUL_H64.value, InternalOp.OP_MUL_H32.value]:
+ if int_op in [MicrOp.OP_MUL_H64.value, MicrOp.OP_MUL_H32.value]:
print ("mul op")
if rc_en & rc_ok:
asmop += "."
if lk:
asmop += "l"
print ("int_op", int_op)
- if int_op in [InternalOp.OP_B.value, InternalOp.OP_BC.value]:
+ if int_op in [MicrOp.OP_B.value, MicrOp.OP_BC.value]:
AA = yield self.dec2.dec.fields.FormI.AA[0:-1]
print ("AA", AA)
if AA:
asmop += "a"
- if int_op == InternalOp.OP_MFCR.value:
+ if int_op == MicrOp.OP_MFCR.value:
dec_insn = yield self.dec2.e.do.insn
if dec_insn & (1<<20) != 0: # sigh
asmop = 'mfocrf'
asmop = 'mfcr'
# XXX TODO: for whatever weird reason this doesn't work
# https://bugs.libre-soc.org/show_bug.cgi?id=390
- if int_op == InternalOp.OP_MTCRF.value:
+ if int_op == MicrOp.OP_MTCRF.value:
dec_insn = yield self.dec2.e.do.insn
if dec_insn & (1<<20) != 0: # sigh
asmop = 'mtocrf'
from collections import namedtuple
from nmigen import Module, Elaboratable, Signal, Cat, Mux
from nmigen.cli import rtlil
-from soc.decoder.power_enums import (Function, Form, InternalOp,
+from soc.decoder.power_enums import (Function, Form, MicrOp,
In1Sel, In2Sel, In3Sel, OutSel,
RC, LdstLen, LDSTMode, CryIn, get_csv,
single_bit_flags, CRInSel,
def __init__(self, incl_asm=True):
self.function_unit = Signal(Function, reset_less=True)
- self.internal_op = Signal(InternalOp, reset_less=True)
+ self.internal_op = Signal(MicrOp, reset_less=True)
self.form = Signal(Form, reset_less=True)
if incl_asm: # for simulator only
self.asmcode = Signal(8, reset_less=True)
ldst_mode = LDSTMode[ldst_mode]
res = [self.function_unit.eq(Function[row['unit']]),
self.form.eq(Form[row['form']]),
- self.internal_op.eq(InternalOp[row['internal op']]),
+ self.internal_op.eq(MicrOp[row['internal op']]),
self.in1_sel.eq(In1Sel[row['in1']]),
self.in2_sel.eq(In2Sel[row['in2']]),
self.in3_sel.eq(In3Sel[row['in3']]),
from soc.decoder.power_regspec_map import regspec_decode_read
from soc.decoder.power_regspec_map import regspec_decode_write
from soc.decoder.power_decoder import create_pdecode
-from soc.decoder.power_enums import (InternalOp, CryIn, Function,
+from soc.decoder.power_enums import (MicrOp, CryIn, Function,
CRInSel, CROutSel,
LdstLen, In1Sel, In2Sel, In3Sel,
OutSel, SPR, RC)
comb = m.d.comb
Signal = is_priv_insn(reset_less=True)
with m.Switch(op):
- with m.Case(InternalOp.OP_ATTN) : comb += is_priv_insn.eq(1)
- with m.Case(InternalOp.OP_MFMSR) : comb += is_priv_insn.eq(1)
- with m.Case(InternalOp.OP_MTMSRD): comb += is_priv_insn.eq(1)
- with m.Case(InternalOp.OP_MTMSR): comb += is_priv_insn.eq(1)
- with m.Case(InternalOp.OP_RFID) : comb += is_priv_insn.eq(1)
- with m.Case(InternalOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
+ with m.Case(MicrOp.OP_ATTN) : comb += is_priv_insn.eq(1)
+ with m.Case(MicrOp.OP_MFMSR) : comb += is_priv_insn.eq(1)
+ with m.Case(MicrOp.OP_MTMSRD): comb += is_priv_insn.eq(1)
+ with m.Case(MicrOp.OP_MTMSR): comb += is_priv_insn.eq(1)
+ with m.Case(MicrOp.OP_RFID) : comb += is_priv_insn.eq(1)
+ with m.Case(MicrOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
with m.If(op == OP_MFSPR | op == OP_MTSPR):
with m.If(insn[20]): # field XFX.spr[-1] i think
comb += is_priv_insn.eq(1)
# decode Fast-SPR based on instruction type
op = self.dec.op
# BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeOut
- with m.If(op.internal_op == InternalOp.OP_BC):
+ with m.If(op.internal_op == MicrOp.OP_BC):
with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
comb += self.fast_out.ok.eq(1)
- with m.Elif(op.internal_op == InternalOp.OP_BCREG):
+ with m.Elif(op.internal_op == MicrOp.OP_BCREG):
xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
xo5 = self.dec.FormXL.XO[5] # 3.0B p38
with m.If(xo9 & ~xo5):
comb += self.fast_out.ok.eq(1)
# MFSPR move from SPRs
- with m.If(op.internal_op == InternalOp.OP_MFSPR):
+ with m.If(op.internal_op == MicrOp.OP_MFSPR):
spr = Signal(10, reset_less=True)
comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
with m.Switch(spr):
op = self.dec.op
# BCREG implicitly uses LR or TAR for 2nd reg
# CTR however is already in fast_spr1 *not* 2.
- with m.If(op.internal_op == InternalOp.OP_BCREG):
+ with m.If(op.internal_op == MicrOp.OP_BCREG):
xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
xo5 = self.dec.FormXL.XO[5] # 3.0B p38
with m.If(~xo9):
spr = Signal(10, reset_less=True)
comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
# TODO MTSPR 1st spr (fast)
- with m.If(op.internal_op == InternalOp.OP_MTSPR):
+ with m.If(op.internal_op == MicrOp.OP_MTSPR):
with m.Switch(spr):
# fast SPRs
with m.Case(SPR.CTR.value):
# BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeA
op = self.dec.op
- with m.If((op.internal_op == InternalOp.OP_BC) |
- (op.internal_op == InternalOp.OP_BCREG)):
+ with m.If((op.internal_op == MicrOp.OP_BC) |
+ (op.internal_op == MicrOp.OP_BCREG)):
with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
comb += self.fast_out.ok.eq(1)
# RFID 1st spr (fast)
- with m.If(op.internal_op == InternalOp.OP_RFID):
+ with m.If(op.internal_op == MicrOp.OP_RFID):
comb += self.fast_out.data.eq(FastRegs.SRR0) # constant: SRR0
comb += self.fast_out.ok.eq(1)
# B, BC or BCREG: potential implicit register (LR) output
# these give bl, bcl, bclrl, etc.
op = self.dec.op
- with m.If((op.internal_op == InternalOp.OP_BC) |
- (op.internal_op == InternalOp.OP_B) |
- (op.internal_op == InternalOp.OP_BCREG)):
+ with m.If((op.internal_op == MicrOp.OP_BC) |
+ (op.internal_op == MicrOp.OP_B) |
+ (op.internal_op == MicrOp.OP_BCREG)):
with m.If(self.lk): # "link" mode
comb += self.fast_out.data.eq(FastRegs.LR) # constant: LR
comb += self.fast_out.ok.eq(1)
# RFID 2nd spr (fast)
- with m.If(op.internal_op == InternalOp.OP_RFID):
+ with m.If(op.internal_op == MicrOp.OP_RFID):
comb += self.fast_out.data.eq(FastRegs.SRR1) # constant: SRR1
comb += self.fast_out.ok.eq(1)
comb = m.d.comb
op = self.dec.op
- with m.If((op.internal_op == InternalOp.OP_MUL_H64) |
- (op.internal_op == InternalOp.OP_MUL_H32)):
+ with m.If((op.internal_op == MicrOp.OP_MUL_H64) |
+ (op.internal_op == MicrOp.OP_MUL_H32)):
# mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
pass
with m.Else():
# sigh this is exactly the sort of thing for which the
# decoder is designed to not need. MTSPR, MFSPR and others need
# access to the XER bits. however setting e.oe is not appropriate
- with m.If(op.internal_op == InternalOp.OP_MFSPR):
+ with m.If(op.internal_op == MicrOp.OP_MFSPR):
comb += e.xer_in.eq(1)
- with m.If(op.internal_op == InternalOp.OP_MTSPR):
+ with m.If(op.internal_op == MicrOp.OP_MTSPR):
comb += e.xer_out.eq(1)
# set the trapaddr to 0x700 for a td/tw/tdi/twi operation
- with m.If(op.internal_op == InternalOp.OP_TRAP):
+ with m.If(op.internal_op == MicrOp.OP_TRAP):
comb += do.trapaddr.eq(0x70) # addr=0x700 (strip first nibble)
# illegal instruction must redirect to trap. this is done by
# *overwriting* the decoded instruction and starting again.
# (note: the same goes for interrupts and for privileged operations,
# just with different trapaddr and traptype)
- with m.If(op.internal_op == InternalOp.OP_ILLEGAL):
+ with m.If(op.internal_op == MicrOp.OP_ILLEGAL):
# illegal instruction trap
self.trap(m, TT_ILLEG, 0x700)
# trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
# Note: OP_SC could actually be modified to just be a trap
- with m.If((do.insn_type == InternalOp.OP_TRAP) |
- (do.insn_type == InternalOp.OP_SC)):
+ with m.If((do.insn_type == MicrOp.OP_TRAP) |
+ (do.insn_type == MicrOp.OP_SC)):
# TRAP write fast1 = SRR0
comb += e.write_fast1.data.eq(FastRegs.SRR0) # constant: SRR0
comb += e.write_fast1.ok.eq(1)
comb += e.write_fast2.ok.eq(1)
# RFID: needs to read SRR0/1
- with m.If(do.insn_type == InternalOp.OP_RFID):
+ with m.If(do.insn_type == MicrOp.OP_RFID):
# TRAP read fast1 = SRR0
comb += e.read_fast1.data.eq(FastRegs.SRR0) # constant: SRR0
comb += e.read_fast1.ok.eq(1)
comb += e.eq(0) # reset eeeeeverything
# start again
comb += do.insn.eq(self.dec.opcode_in)
- comb += do.insn_type.eq(InternalOp.OP_TRAP)
+ comb += do.insn_type.eq(MicrOp.OP_TRAP)
comb += do.fn_unit.eq(Function.TRAP)
comb += do.trapaddr.eq(trapaddr >> 4) # cut bottom 4 bits
comb += do.traptype.eq(traptype) # request type
# Internal Operation numbering. Add new opcodes here (FPADD, FPMUL etc.)
@unique
-class InternalOp(Enum):
+class MicrOp(Enum):
OP_ILLEGAL = 0 # important that this is zero (see power_decoder.py)
OP_NOP = 1
OP_ADD = 2
from nmutil.formaltest import FHDLTestCase
import unittest
from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_enums import (Function, InternalOp,
+from soc.decoder.power_enums import (Function, MicrOp,
In1Sel, In2Sel, In3Sel,
OutSel, RC, LdstLen, CryIn,
single_bit_flags, Form, SPR,
class RegRegOp:
def __init__(self):
self.ops = {
- "add": InternalOp.OP_ADD,
- "and": InternalOp.OP_AND,
- "or": InternalOp.OP_OR,
- "add.": InternalOp.OP_ADD,
- "lwzx": InternalOp.OP_LOAD,
- "stwx": InternalOp.OP_STORE,
+ "add": MicrOp.OP_ADD,
+ "and": MicrOp.OP_AND,
+ "or": MicrOp.OP_OR,
+ "add.": MicrOp.OP_ADD,
+ "lwzx": MicrOp.OP_LOAD,
+ "stwx": MicrOp.OP_STORE,
}
self.opcodestr = random.choice(list(self.ops.keys()))
self.opcode = self.ops[self.opcodestr]
return string
def check_results(self, pdecode2):
- if self.opcode == InternalOp.OP_STORE:
+ if self.opcode == MicrOp.OP_STORE:
r1sel = yield pdecode2.e.read_reg3.data
else:
r1sel = yield pdecode2.e.write_reg.data
def __init__(self):
super().__init__()
self.ops = {
- "addi": InternalOp.OP_ADD,
- "addis": InternalOp.OP_ADD,
- "andi.": InternalOp.OP_AND,
- "ori": InternalOp.OP_OR,
+ "addi": MicrOp.OP_ADD,
+ "addis": MicrOp.OP_ADD,
+ "andi.": MicrOp.OP_AND,
+ "ori": MicrOp.OP_OR,
}
self.opcodestr = random.choice(list(self.ops.keys()))
self.opcode = self.ops[self.opcodestr]
def __init__(self):
super().__init__()
self.ops = {
- "lwz": InternalOp.OP_LOAD,
- "stw": InternalOp.OP_STORE,
- "lwzu": InternalOp.OP_LOAD,
- "stwu": InternalOp.OP_STORE,
- "lbz": InternalOp.OP_LOAD,
- "lhz": InternalOp.OP_LOAD,
- "stb": InternalOp.OP_STORE,
- "sth": InternalOp.OP_STORE,
+ "lwz": MicrOp.OP_LOAD,
+ "stw": MicrOp.OP_STORE,
+ "lwzu": MicrOp.OP_LOAD,
+ "stwu": MicrOp.OP_STORE,
+ "lbz": MicrOp.OP_LOAD,
+ "lhz": MicrOp.OP_LOAD,
+ "stb": MicrOp.OP_STORE,
+ "sth": MicrOp.OP_STORE,
}
self.opcodestr = random.choice(list(self.ops.keys()))
self.opcode = self.ops[self.opcodestr]
def check_results(self, pdecode2):
print("Check")
r2sel = yield pdecode2.e.read_reg1.data
- if self.opcode == InternalOp.OP_STORE:
+ if self.opcode == MicrOp.OP_STORE:
r1sel = yield pdecode2.e.read_reg3.data
else:
r1sel = yield pdecode2.e.write_reg.data
class CmpRegOp:
def __init__(self):
self.ops = {
- "cmp": InternalOp.OP_CMP,
+ "cmp": MicrOp.OP_CMP,
}
self.opcodestr = random.choice(list(self.ops.keys()))
self.opcode = self.ops[self.opcodestr]
class RotateOp:
def __init__(self):
self.ops = {
- "rlwinm": InternalOp.OP_CMP,
- "rlwnm": InternalOp.OP_CMP,
- "rlwimi": InternalOp.OP_CMP,
- "rlwinm.": InternalOp.OP_CMP,
- "rlwnm.": InternalOp.OP_CMP,
- "rlwimi.": InternalOp.OP_CMP,
+ "rlwinm": MicrOp.OP_CMP,
+ "rlwnm": MicrOp.OP_CMP,
+ "rlwimi": MicrOp.OP_CMP,
+ "rlwinm.": MicrOp.OP_CMP,
+ "rlwnm.": MicrOp.OP_CMP,
+ "rlwimi.": MicrOp.OP_CMP,
}
self.opcodestr = random.choice(list(self.ops.keys()))
self.opcode = self.ops[self.opcodestr]
class Branch:
def __init__(self):
self.ops = {
- "b": InternalOp.OP_B,
- "bl": InternalOp.OP_B,
- "ba": InternalOp.OP_B,
- "bla": InternalOp.OP_B,
+ "b": MicrOp.OP_B,
+ "bl": MicrOp.OP_B,
+ "ba": MicrOp.OP_B,
+ "bla": MicrOp.OP_B,
}
self.opcodestr = random.choice(list(self.ops.keys()))
self.opcode = self.ops[self.opcodestr]
class BranchCond:
def __init__(self):
self.ops = {
- "bc": InternalOp.OP_B,
- "bcl": InternalOp.OP_B,
- "bca": InternalOp.OP_B,
- "bcla": InternalOp.OP_B,
+ "bc": MicrOp.OP_B,
+ "bcl": MicrOp.OP_B,
+ "bca": MicrOp.OP_B,
+ "bcla": MicrOp.OP_B,
}
# Given in Figure 40 "BO field encodings" in section 2.4, page
# 33 of the Power ISA v3.0B manual
class BranchRel:
def __init__(self):
self.ops = {
- "bclr": InternalOp.OP_B,
- "bcctr": InternalOp.OP_B,
- "bclrl": InternalOp.OP_B,
- "bcctrl": InternalOp.OP_B,
+ "bclr": MicrOp.OP_B,
+ "bcctr": MicrOp.OP_B,
+ "bclrl": MicrOp.OP_B,
+ "bcctrl": MicrOp.OP_B,
}
# Given in Figure 40 "BO field encodings" in section 2.4, page
# 33 of the Power ISA v3.0B manual
class CROp:
def __init__(self):
self.ops = {
- "crand": InternalOp.OP_CROP,
+ "crand": MicrOp.OP_CROP,
}
# Given in Figure 40 "BO field encodings" in section 2.4, page
# 33 of the Power ISA v3.0B manual
import os
import unittest
from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_enums import (Function, InternalOp,
+from soc.decoder.power_enums import (Function, MicrOp,
In1Sel, In2Sel, In3Sel,
CRInSel, CROutSel,
OutSel, RC, LdstLen, CryIn,
comb = m.d.comb
opcode = Signal(32)
function_unit = Signal(Function)
- internal_op = Signal(InternalOp)
+ internal_op = Signal(MicrOp)
in1_sel = Signal(In1Sel)
in2_sel = Signal(In2Sel)
in3_sel = Signal(In3Sel)
yield Delay(1e-6)
signals = [(function_unit, Function, 'unit'),
- (internal_op, InternalOp, 'internal op'),
+ (internal_op, MicrOp, 'internal op'),
(in1_sel, In1Sel, 'in1'),
(in2_sel, In2Sel, 'in2'),
(in3_sel, In3Sel, 'in3'),
from nmigen.compat.sim import run_simulation
from nmigen.back.pysim import Simulator, Settle
-from soc.decoder.power_enums import InternalOp, Function, CryIn
+from soc.decoder.power_enums import MicrOp, Function, CryIn
from soc.fu.alu.alu_input_record import CompALUOpSubset
from soc.fu.cr.cr_input_record import CompCROpSubset
with m.If(self.p.valid_i):
# as this is a "fake" pipeline, just grab the output right now
- with m.If(self.op.insn_type == InternalOp.OP_ADD):
+ with m.If(self.op.insn_type == MicrOp.OP_ADD):
m.d.sync += alu_r.eq(add.o)
- with m.Elif(self.op.insn_type == InternalOp.OP_MUL_L64):
+ with m.Elif(self.op.insn_type == MicrOp.OP_MUL_L64):
m.d.sync += alu_r.eq(mul.o)
- with m.Elif(self.op.insn_type == InternalOp.OP_SHR):
+ with m.Elif(self.op.insn_type == MicrOp.OP_SHR):
m.d.sync += alu_r.eq(shf.o)
# SUB is zero-delay, no need to register
# NOTE: all of these are fake, just something to test
# MUL, to take 5 instructions
- with m.If(self.op.insn_type == InternalOp.OP_MUL_L64):
+ with m.If(self.op.insn_type == MicrOp.OP_MUL_L64):
m.d.sync += self.counter.eq(5)
# SHIFT to take 1, straight away
- with m.Elif(self.op.insn_type == InternalOp.OP_SHR):
+ with m.Elif(self.op.insn_type == MicrOp.OP_SHR):
m.d.sync += self.counter.eq(1)
# ADD/SUB to take 3
- with m.Elif(self.op.insn_type == InternalOp.OP_ADD):
+ with m.Elif(self.op.insn_type == MicrOp.OP_ADD):
m.d.sync += self.counter.eq(3)
# others to take no delay
with m.Else():
def alu_sim(dut):
- result = yield from run_op(dut, 5, 3, InternalOp.OP_ADD)
+ result = yield from run_op(dut, 5, 3, MicrOp.OP_ADD)
print ("alu_sim add", result)
assert (result == 8)
- result = yield from run_op(dut, 2, 3, InternalOp.OP_MUL_L64)
+ result = yield from run_op(dut, 2, 3, MicrOp.OP_MUL_L64)
print ("alu_sim mul", result)
assert (result == 6)
- result = yield from run_op(dut, 5, 3, InternalOp.OP_ADD, inv_a=1)
+ result = yield from run_op(dut, 5, 3, MicrOp.OP_ADD, inv_a=1)
print ("alu_sim add-inv", result)
assert (result == 65533)
# test zero-delay ALU
# don't have OP_SUB, so use any other
- result = yield from run_op(dut, 5, 3, InternalOp.OP_NOP)
+ result = yield from run_op(dut, 5, 3, MicrOp.OP_NOP)
print ("alu_sim sub", result)
assert (result == 2)
- result = yield from run_op(dut, 13, 2, InternalOp.OP_SHR)
+ result = yield from run_op(dut, 13, 2, MicrOp.OP_SHR)
print ("alu_sim shr", result)
assert (result == 3)
# note that, for this test, we do not wait for the result to be ready,
# before presenting the next input
# 5 + 3
- yield from send(5, 3, InternalOp.OP_ADD)
+ yield from send(5, 3, MicrOp.OP_ADD)
yield
yield
# 2 * 3
- yield from send(2, 3, InternalOp.OP_MUL_L64)
+ yield from send(2, 3, MicrOp.OP_MUL_L64)
# (-5) + 3
- yield from send(5, 3, InternalOp.OP_ADD, inv_a=1)
+ yield from send(5, 3, MicrOp.OP_ADD, inv_a=1)
yield
# 5 - 3
# note that this is a zero-delay operation
- yield from send(5, 3, InternalOp.OP_NOP)
+ yield from send(5, 3, MicrOp.OP_NOP)
yield
yield
# 13 >> 2
- yield from send(13, 2, InternalOp.OP_SHR)
+ yield from send(13, 2, MicrOp.OP_SHR)
def consumer():
# receive and check results, interspersed with wait states
from nmutil.latch import SRLatch, latchregister
from soc.decoder.power_decoder2 import Data
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
from soc.experiment.alu_hier import CompALUOpSubset
def scoreboard_sim(dut):
- result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=0,
+ result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, inv_a=0,
imm=8, imm_ok=1)
assert result == 13
- result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=1)
+ result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, inv_a=1)
assert result == 65532
- result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD)
+ result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD)
assert result == 7
from soc.experiment.l0_cache import PortInterface
from soc.fu.regspec import RegSpecAPI
-from soc.decoder.power_enums import InternalOp, Function, LDSTMode
+from soc.decoder.power_enums import MicrOp, Function, LDSTMode
from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
from soc.decoder.power_decoder2 import Data
sync += alu_ok.eq(alu_valid) # keep ack in sync with EA
# decode bits of operand (latched)
- comb += op_is_st.eq(oper_r.insn_type == InternalOp.OP_STORE) # ST
- comb += op_is_ld.eq(oper_r.insn_type == InternalOp.OP_LOAD) # LD
+ comb += op_is_st.eq(oper_r.insn_type == MicrOp.OP_STORE) # ST
+ comb += op_is_ld.eq(oper_r.insn_type == MicrOp.OP_LOAD) # LD
op_is_update = oper_r.ldst_mode == LDSTMode.update # UPDATE
op_is_cix = oper_r.ldst_mode == LDSTMode.cix # cache-inhibit
comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i)
def store(dut, src1, src2, src3, imm, imm_ok=True, update=False,
byterev=True):
print ("ST", src1, src2, src3, imm, imm_ok, update)
- yield dut.oper_i.insn_type.eq(InternalOp.OP_STORE)
+ yield dut.oper_i.insn_type.eq(MicrOp.OP_STORE)
yield dut.oper_i.data_len.eq(2) # half-word
yield dut.oper_i.byte_reverse.eq(byterev)
yield dut.src1_i.eq(src1)
def load(dut, src1, src2, imm, imm_ok=True, update=False, zero_a=False,
byterev=True):
print ("LD", src1, src2, imm, imm_ok, update)
- yield dut.oper_i.insn_type.eq(InternalOp.OP_LOAD)
+ yield dut.oper_i.insn_type.eq(MicrOp.OP_LOAD)
yield dut.oper_i.data_len.eq(2) # half-word
yield dut.oper_i.byte_reverse.eq(byterev)
yield dut.src1_i.eq(src1)
from nmutil.latch import SRLatch, latchregister
from soc.decoder.power_decoder2 import Data
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
from soc.regfile.regfile import ortreereduce
from nmutil.util import treereduce
from soc.experiment.alu_hier import ALU, BranchALU, CompALUOpSubset
-from soc.decoder.power_enums import InternalOp, Function
+from soc.decoder.power_enums import MicrOp, Function
from soc.decoder.power_decoder import (create_pdecode)
from soc.decoder.power_decoder2 import (PowerDecode2)
from soc.simulator.program import Program
instrs.append((1, 7, 2, 2, 0, 0, (0, 0)))
if True:
- instrs.append((2, 3, 3, InternalOp.OP_ADD, Function.ALU,
+ instrs.append((2, 3, 3, MicrOp.OP_ADD, Function.ALU,
0, 0, (0, 0)))
- instrs.append((5, 3, 3, InternalOp.OP_ADD, Function.ALU,
+ instrs.append((5, 3, 3, MicrOp.OP_ADD, Function.ALU,
0, 0, (0, 0)))
if False:
- instrs.append((3, 5, 5, InternalOp.OP_MUL_L64, Function.ALU,
+ instrs.append((3, 5, 5, MicrOp.OP_MUL_L64, Function.ALU,
1, 7, (0, 0)))
if False:
- instrs.append((2, 3, 3, InternalOp.OP_ADD, Function.ALU,
+ instrs.append((2, 3, 3, MicrOp.OP_ADD, Function.ALU,
0, 0, (0, 0)))
if False:
from soc.experiment.alu_hier import ALU, BranchALU
from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.decoder.power_enums import InternalOp, Function
+from soc.decoder.power_enums import MicrOp, Function
from soc.decoder.power_decoder import (create_pdecode)
from soc.decoder.power_decoder2 import (PowerDecode2)
from soc.decoder.power_decoder2 import Decode2ToExecute1Type
instrs.append((1, 7, 2, 2, 0, 0, (0, 0)))
if True:
- instrs.append((2, 3, 3, InternalOp.OP_ADD, Function.ALU,
+ instrs.append((2, 3, 3, MicrOp.OP_ADD, Function.ALU,
0, 0, (0, 0)))
- instrs.append((5, 3, 3, InternalOp.OP_ADD, Function.ALU,
+ instrs.append((5, 3, 3, MicrOp.OP_ADD, Function.ALU,
0, 0, (0, 0)))
if False:
- instrs.append((3, 5, 5, InternalOp.OP_MUL_L64, Function.ALU,
+ instrs.append((3, 5, 5, MicrOp.OP_MUL_L64, Function.ALU,
1, 7, (0, 0)))
if False:
- instrs.append((2, 3, 3, InternalOp.OP_ADD, Function.ALU,
+ instrs.append((2, 3, 3, MicrOp.OP_ADD, Function.ALU,
0, 0, (0, 0)))
if False:
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
from random import randint, seed
from copy import deepcopy
src2 = imm
else:
src2 = self.regs[src2] & maxbits
- if op == InternalOp.OP_ADD:
+ if op == MicrOp.OP_ADD:
val = src1 + src2
- elif op == InternalOp.OP_MUL_L64:
+ elif op == MicrOp.OP_MUL_L64:
val = src1 * src2
print ("mul src1, src2", src1, src2, val)
elif op == ISUB:
from nmigen.cli import rtlil
from nmigen import Module
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
from soc.experiment.compalu_multi import MultiCompUnit
from soc.experiment.alu_hier import ALU, DummyALU
def scoreboard_sim_dummy(dut):
- result = yield from op_sim(dut, 5, 2, InternalOp.OP_NOP, inv_a=0,
+ result = yield from op_sim(dut, 5, 2, MicrOp.OP_NOP, inv_a=0,
imm=8, imm_ok=1)
assert result == 5, result
- result = yield from op_sim(dut, 9, 2, InternalOp.OP_NOP, inv_a=0,
+ result = yield from op_sim(dut, 9, 2, MicrOp.OP_NOP, inv_a=0,
imm=8, imm_ok=1)
assert result == 9, result
def scoreboard_sim(dut):
- result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=0,
+ result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, inv_a=0,
imm=8, imm_ok=1)
assert result == 13
- result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD)
+ result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD)
assert result == 7
- result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=1)
+ result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, inv_a=1)
assert result == 65532
- result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, zero_a=1,
+ result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, zero_a=1,
imm=8, imm_ok=1)
assert result == 8
- result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, zero_a=1)
+ result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, zero_a=1)
assert result == 2
# test combinatorial zero-delay operation
# In the test ALU, any operation other than ADD, MUL or SHR
# is zero-delay, and do a subtraction.
- result = yield from op_sim(dut, 5, 2, InternalOp.OP_NOP)
+ result = yield from op_sim(dut, 5, 2, MicrOp.OP_NOP)
assert result == 3
def driver(self):
print("Begin parallel test.")
- yield from self.operation(5, 2, InternalOp.OP_ADD)
+ yield from self.operation(5, 2, MicrOp.OP_ADD)
def operation(self, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0,
rdmaskn=(0, 0)):
from nmigen.hdl.rec import Record, Layout
-from soc.decoder.power_enums import InternalOp, Function, CryIn
+from soc.decoder.power_enums import MicrOp, Function, CryIn
class CompALUOpSubset(Record):
grab subsets.
"""
def __init__(self, name=None):
- layout = (('insn_type', InternalOp),
+ layout = (('insn_type', MicrOp),
('fn_unit', Function),
('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
('rc', Layout((("rc", 1), ("rc_ok", 1)))), # Data
from soc.fu.alu.input_stage import ALUInputStage
from soc.fu.alu.pipe_data import ALUPipeSpec
from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
import unittest
from soc.fu.alu.main_stage import ALUMainStage
from soc.fu.alu.pipe_data import ALUPipeSpec
from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
import unittest
# main assertion of arithmetic operations
with m.Switch(rec.insn_type):
- with m.Case(InternalOp.OP_ADD):
+ with m.Case(MicrOp.OP_ADD):
# check result of 65-bit add-with-carry
comb += Assert(Cat(o, ca_o) == (a + b + ca_in))
comb += ca_ok.eq(1)
comb += o_ok.eq(1)
- with m.Case(InternalOp.OP_EXTS):
+ with m.Case(MicrOp.OP_EXTS):
for i in [1, 2, 4]:
with m.If(rec.data_len == i):
# main part, then sign-bit replicated up
comb += Assert(o[i*8:64] == Repl(a[i*8-1], 64-(i*8)))
comb += o_ok.eq(1)
- with m.Case(InternalOp.OP_CMP):
+ with m.Case(MicrOp.OP_CMP):
# CMP is defined as not taking in carry
comb += Assume(ca_in == 0)
comb += Assert(o == (a+b)[0:64])
- with m.Case(InternalOp.OP_CMPEQB):
+ with m.Case(MicrOp.OP_CMPEQB):
src1 = a[0:8]
eqs = Signal(8)
for i in range(8):
from soc.fu.alu.output_stage import ALUOutputStage
from soc.fu.alu.pipe_data import ALUPipeSpec
from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
import unittest
# sigh. see https://bugs.libre-soc.org/show_bug.cgi?id=305#c61
# for OP_CMP we do b-a rather than a-b (just like ADD) and
# then invert the *test condition*.
- with m.If(rec.insn_type == InternalOp.OP_CMP):
+ with m.If(rec.insn_type == MicrOp.OP_CMP):
comb += Assert(cr_out[3] == 1)
with m.Else():
comb += Assert(cr_out[2] == 1)
with m.Elif(o_signed < 0):
# ditto as above
- with m.If(rec.insn_type == InternalOp.OP_CMP):
+ with m.If(rec.insn_type == MicrOp.OP_CMP):
comb += Assert(cr_out[2] == 1)
with m.Else():
comb += Assert(cr_out[3] == 1)
from nmutil.extend import exts
from soc.fu.alu.pipe_data import ALUInputData, ALUOutputData
from ieee754.part.partsig import PartitionedSignal
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
# microwatt calc_ov function.
add_a = Signal(a.width + 2, reset_less=True)
add_b = Signal(a.width + 2, reset_less=True)
add_o = Signal(a.width + 2, reset_less=True)
- with m.If((op.insn_type == InternalOp.OP_ADD) |
- (op.insn_type == InternalOp.OP_CMP)):
+ with m.If((op.insn_type == MicrOp.OP_ADD) |
+ (op.insn_type == MicrOp.OP_CMP)):
# in bit 0, 1+carry_in creates carry into bit 1 and above
comb += add_a.eq(Cat(cry_i[0], a, Const(0, 1)))
comb += add_b.eq(Cat(Const(1, 1), b, Const(0, 1)))
with m.Switch(op.insn_type):
#### CMP, CMPL ####
- with m.Case(InternalOp.OP_CMP):
+ with m.Case(MicrOp.OP_CMP):
# this is supposed to be inverted (b-a, not a-b)
# however we have a trick: instead of adding either 2x 64-bit
# MUXes to invert a and b, or messing with a 64-bit output,
comb += o.ok.eq(0) # use o.data but do *not* actually output
#### add ####
- with m.Case(InternalOp.OP_ADD):
+ with m.Case(MicrOp.OP_ADD):
# bit 0 is not part of the result, top bit is the carry-out
comb += o.data.eq(add_o[1:-1])
comb += o.ok.eq(1) # output register
comb += ov_o.ok.eq(1)
#### exts (sign-extend) ####
- with m.Case(InternalOp.OP_EXTS):
+ with m.Case(MicrOp.OP_EXTS):
with m.If(op.data_len == 1):
comb += o.data.eq(exts(a, 8, 64))
with m.If(op.data_len == 2):
comb += o.ok.eq(1) # output register
#### cmpeqb ####
- with m.Case(InternalOp.OP_CMPEQB):
+ with m.Case(MicrOp.OP_CMPEQB):
eqs = Signal(8, reset_less=True)
src1 = Signal(8, reset_less=True)
comb += src1.eq(a[0:8])
from soc.fu.alu.pipe_data import ALUInputData, ALUOutputData
from soc.fu.common_output_stage import CommonOutputStage
from ieee754.part.partsig import PartitionedSignal
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
class ALUOutputStage(CommonOutputStage):
from soc.decoder.isa.caller import ISACaller, special_sprs
from soc.decoder.power_decoder import (create_pdecode)
from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
+from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)
from soc.decoder.selectable_int import SelectableInt
from soc.simulator.program import Program
from soc.decoder.isa.all import ISA
from nmigen.hdl.rec import Record, Layout
-from soc.decoder.power_enums import InternalOp, Function, CryIn
+from soc.decoder.power_enums import MicrOp, Function, CryIn
class CompBROpSubset(Record):
grab subsets.
"""
def __init__(self, name=None):
- layout = (('insn_type', InternalOp),
+ layout = (('insn_type', MicrOp),
('fn_unit', Function),
('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
('lk', 1),
from soc.fu.alu.input_stage import ALUInputStage
from soc.fu.alu.pipe_data import ALUPipeSpec
from soc.fu.branch.br_input_record import CompBROpSubset
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
import unittest
comb += Assert(dut.o.a == a)
with m.If(rec.imm_data.imm_ok &
- ~(rec.insn_type == InternalOp.OP_RLC)):
+ ~(rec.insn_type == MicrOp.OP_RLC)):
comb += Assert(dut.o.b == rec.imm_data.imm)
with m.Else():
comb += Assert(dut.o.b == b)
from soc.fu.branch.main_stage import BranchMainStage
from soc.fu.alu.pipe_data import ALUPipeSpec
from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
import unittest
with m.Switch(rec.insn_type):
#### b ####
- with m.Case(InternalOp.OP_B):
+ with m.Case(MicrOp.OP_B):
# Extract target address
LI = i_fields.LI[0:-1]
imm = exts(LI, LI.shape().width, 64-2) * 4
comb += Assert(dut.o.ctr.ok == 0)
#### bc ####
- with m.Case(InternalOp.OP_BC):
+ with m.Case(MicrOp.OP_BC):
# Assert that branches are conditional
comb += Assert(nia_o.ok == (cond_ok & ctr_ok))
with m.Else():
comb += Assert(dut.o.ctr.ok == 0)
#### bctar/bcctr/bclr ####
- with m.Case(InternalOp.OP_BCREG):
+ with m.Case(MicrOp.OP_BCREG):
# assert that the condition is good
comb += Assert(nia_o.ok == (cond_ok & ctr_ok))
from nmutil.pipemodbase import PipeModBase
from nmutil.extend import exts
from soc.fu.branch.pipe_data import BranchInputData, BranchOutputData
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
from soc.decoder.power_fields import DecodeFields
from soc.decoder.power_fieldsn import SignalBitRange
br_taken = Signal(reset_less=True)
# Handle absolute or relative branches
- with m.If(AA | (op.insn_type == InternalOp.OP_BCREG)):
+ with m.If(AA | (op.insn_type == MicrOp.OP_BCREG)):
comb += br_addr.eq(br_imm_addr)
with m.Else():
comb += br_addr.eq(br_imm_addr + cia)
### Main Switch Statement ###
with m.Switch(op.insn_type):
#### branch ####
- with m.Case(InternalOp.OP_B):
+ with m.Case(MicrOp.OP_B):
LI = i_fields.LI[0:-1]
comb += br_imm_addr.eq(br_ext(LI))
comb += br_taken.eq(1)
#### branch conditional ####
- with m.Case(InternalOp.OP_BC):
+ with m.Case(MicrOp.OP_BC):
BD = b_fields.BD[0:-1]
comb += br_imm_addr.eq(br_ext(BD))
comb += br_taken.eq(bc_taken)
comb += ctr_o.ok.eq(ctr_write)
#### branch conditional reg ####
- with m.Case(InternalOp.OP_BCREG):
+ with m.Case(MicrOp.OP_BCREG):
xo = self.fields.FormXL.XO[0:-1]
with m.If(xo[9] & ~xo[5]):
comb += br_imm_addr.eq(Cat(Const(0, 2), fast1[2:]))
from soc.decoder.isa.caller import ISACaller, special_sprs
from soc.decoder.power_decoder import (create_pdecode)
from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import (XER_bits, Function, InternalOp)
+from soc.decoder.power_enums import (XER_bits, Function, MicrOp)
from soc.decoder.selectable_int import SelectableInt
from soc.simulator.program import Program
from soc.decoder.isa.all import ISA
# generation for subtraction, should happen here
from nmigen import (Module, Signal)
from nmutil.pipemodbase import PipeModBase
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
from soc.decoder.power_enums import CryIn
from nmigen import (Module, Signal, Cat, Const)
from nmutil.pipemodbase import PipeModBase
from ieee754.part.partsig import PartitionedSignal
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
class CommonOutputStage(PipeModBase):
# that can be used as a test of whether to invert the +ve/-ve test
# see https://bugs.libre-soc.org/show_bug.cgi?id=305#c60
- comb += is_cmp.eq(op.insn_type == InternalOp.OP_CMP)
- comb += is_cmpeqb.eq(op.insn_type == InternalOp.OP_CMPEQB)
+ comb += is_cmp.eq(op.insn_type == MicrOp.OP_CMP)
+ comb += is_cmpeqb.eq(op.insn_type == MicrOp.OP_CMPEQB)
# nope - if *processor* mode is 32-bit
#with m.If(op.is_32bit):
# comb += msb_test.eq(target[-1] ^ is_cmp) # 64-bit MSB
from soc.experiment.alu_hier import DummyALU
from soc.experiment.compalu_multi import MultiCompUnit
from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
import unittest
class MaskGenTestCase(FHDLTestCase):
yield dut.src1_i.eq(0x5)
yield dut.src2_i.eq(0x5)
yield dut.issue_i.eq(1)
- yield dut.oper_i.insn_type.eq(InternalOp.OP_ADD)
+ yield dut.oper_i.insn_type.eq(MicrOp.OP_ADD)
yield
yield dut.issue_i.eq(0)
yield
from nmigen.hdl.rec import Record, Layout
-from soc.decoder.power_enums import (InternalOp, Function)
+from soc.decoder.power_enums import (MicrOp, Function)
class CompCROpSubset(Record):
grab subsets.
"""
def __init__(self, name=None):
- layout = (('insn_type', InternalOp),
+ layout = (('insn_type', MicrOp),
('fn_unit', Function),
('insn', 32),
('read_cr_whole', 1),
from soc.fu.cr.main_stage import CRMainStage
from soc.fu.alu.pipe_data import ALUPipeSpec
from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
import unittest
with m.Switch(rec.insn_type):
# CR_ISEL takes cr_a
- with m.Case(InternalOp.OP_ISEL):
+ with m.Case(MicrOp.OP_ISEL):
# grab the MSBs of the cr bit selector
bc = Signal(3, reset_less=True)
comb += bc.eq(a_fields.BC[2:5])
# For OP_CROP, we need to input the corresponding CR
# registers for BA, BB, and BT
- with m.Case(InternalOp.OP_CROP):
+ with m.Case(MicrOp.OP_CROP):
# grab the MSBs of the 3 bit selectors
bt = Signal(3, reset_less=True)
ba = Signal(3, reset_less=True)
with m.Else():
comb += cr_output_arr[i].eq(dut.o.cr.data)
- with m.Case(InternalOp.OP_MCRF):
+ with m.Case(MicrOp.OP_MCRF):
# This does a similar thing to OP_CROP above, with
# less inputs. The CR selection fields are already 3
# bits so there's no need to grab only the MSBs
comb += cr_output_arr[i].eq(dut.o.cr.data)
# Set the input similar to OP_MCRF
- with m.Case(InternalOp.OP_SETB):
+ with m.Case(MicrOp.OP_SETB):
comb += dut.i.cr_a.eq(cr_input_arr[bfa])
# For the other two, they take the full CR as input, and
FXM = xfx_fields.FXM[0:-1]
with m.Switch(rec.insn_type):
- with m.Case(InternalOp.OP_MTCRF):
+ with m.Case(MicrOp.OP_MTCRF):
for i in range(8):
with m.If(FXM[i]):
comb += Assert(cr_o[4*i:4*i+4] == a[4*i:4*i+4])
comb += full_cr_o_ok.eq(1)
- with m.Case(InternalOp.OP_MFCR):
+ with m.Case(MicrOp.OP_MFCR):
with m.If(rec.insn[20]): # mfocrf
for i in range(8):
with m.If(FXM[i]):
comb += Assert(o == cr)
comb += o_ok.eq(1)
- with m.Case(InternalOp.OP_MCRF):
+ with m.Case(MicrOp.OP_MCRF):
BF = xl_fields.BF[0:-1]
BFA = xl_fields.BFA[0:-1]
for i in range(4):
comb += Assert(cr_o[i*4:i*4+4] == cr[i*4:i*4+4])
comb += cr_o_ok.eq(1)
- with m.Case(InternalOp.OP_CROP):
+ with m.Case(MicrOp.OP_CROP):
bt = Signal(xl_fields.BT[0:-1].shape(), reset_less=True)
ba = Signal(xl_fields.BA[0:-1].shape(), reset_less=True)
bb = Signal(xl_fields.BB[0:-1].shape(), reset_less=True)
comb += cr_o_ok.eq(1)
- with m.Case(InternalOp.OP_ISEL):
+ with m.Case(MicrOp.OP_ISEL):
# Extract the bit selector of the CR
bc = Signal(a_fields.BC[0:-1].shape(), reset_less=True)
comb += bc.eq(a_fields.BC[0:-1])
comb += Assert(o == Mux(cr_bit, a, b))
comb += o_ok.eq(1)
- with m.Case(InternalOp.OP_SETB):
+ with m.Case(MicrOp.OP_SETB):
with m.If(cr_arr[4*bfa]):
comb += Assert(o == ((1<<64)-1))
with m.Elif(cr_arr[4*bfa+1]):
from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
from nmutil.pipemodbase import PipeModBase
from soc.fu.cr.pipe_data import CRInputData, CROutputData
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
from soc.decoder.power_fields import DecodeFields
from soc.decoder.power_fieldsn import SignalBitRange
with m.Switch(op.insn_type):
##### mcrf #####
- with m.Case(InternalOp.OP_MCRF):
+ with m.Case(MicrOp.OP_MCRF):
# MCRF copies the 4 bits of crA to crB (for instance
# copying cr2 to cr1)
# Since it takes in a 4 bit cr, and outputs a 4 bit
comb += cr_o.ok.eq(1) # indicate "this CR has changed"
# ##### crand, cror, crnor etc. #####
- with m.Case(InternalOp.OP_CROP):
+ with m.Case(MicrOp.OP_CROP):
# crand/cror and friends get decoded to the same opcode, but
# one of the fields inside the instruction is a 4 bit lookup
# table. This lookup table gets indexed by bits a and b from
comb += cr_o.ok.eq(1) # indicate "this CR has changed"
##### mtcrf #####
- with m.Case(InternalOp.OP_MTCRF):
+ with m.Case(MicrOp.OP_MTCRF):
# mtocrf and mtcrf are essentially identical
# put input (RA) - mask-selected - into output CR, leave
# rest of CR alone.
comb += full_cr_o.ok.eq(1) # indicate "this CR has changed"
# ##### mfcr #####
- with m.Case(InternalOp.OP_MFCR):
+ with m.Case(MicrOp.OP_MFCR):
# Ugh. mtocrf and mtcrf have one random bit differentiating
# them. This bit is not in any particular field, so this
# extracts that bit from the instruction
comb += rt_o.ok.eq(1) # indicate "INT reg changed"
# ##### isel #####
- with m.Case(InternalOp.OP_ISEL):
+ with m.Case(MicrOp.OP_ISEL):
# just like in branch, CR0-7 is incoming into cr_a, we
# need to select from the last 2 bits of BC
a_fields = self.fields.FormA
comb += rt_o.eq(Mux(cr_bit, a, b))
comb += rt_o.ok.eq(1) # indicate "INT reg changed"
- with m.Case(InternalOp.OP_SETB):
+ with m.Case(MicrOp.OP_SETB):
with m.If(cr_a[3]):
comb += rt_o.data.eq(-1)
with m.Elif(cr_a[2]):
from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
from nmutil.pipemodbase import PipeModBase
from ieee754.part.partsig import PartitionedSignal
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
from soc.decoder.power_fields import DecodeFields
from soc.decoder.power_fieldsn import SignalBitRange
from soc.fu.logical.main_stage import LogicalMainStage
from soc.fu.alu.pipe_data import ALUPipeSpec
from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
import unittest
# main assertion of arithmetic operations
with m.Switch(rec.insn_type):
- with m.Case(InternalOp.OP_AND):
+ with m.Case(MicrOp.OP_AND):
comb += Assert(dut.o.o == a & b)
- with m.Case(InternalOp.OP_OR):
+ with m.Case(MicrOp.OP_OR):
comb += Assert(dut.o.o == a | b)
- with m.Case(InternalOp.OP_XOR):
+ with m.Case(MicrOp.OP_XOR):
comb += Assert(dut.o.o == a ^ b)
- with m.Case(InternalOp.OP_POPCNT):
+ with m.Case(MicrOp.OP_POPCNT):
with m.If(rec.data_len == 8):
comb += Assert(dut.o.o == self.popcount(a, 64))
with m.If(rec.data_len == 4):
comb += Assert(dut.o.o[i*8:(i+1)*8] ==
self.popcount(a[i*8:(i+1)*8], 8))
- with m.Case(InternalOp.OP_PRTY):
+ with m.Case(MicrOp.OP_PRTY):
with m.If(rec.data_len == 8):
result = 0
for i in range(8):
result_high = result_high ^ a[i*8 + 32]
comb += Assert(dut.o.o[0:32] == result_low)
comb += Assert(dut.o.o[32:64] == result_high)
- with m.Case(InternalOp.OP_CNTZ):
+ with m.Case(MicrOp.OP_CNTZ):
XO = dut.fields.FormX.XO[0:-1]
with m.If(rec.is_32bit):
m.submodules.pe32 = pe32 = PriorityEncoder(32)
from soc.fu.logical.pipe_data import LogicalInputData
from soc.fu.div.pipe_data import DivMulOutputData
from ieee754.part.partsig import PartitionedSignal
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
from soc.decoder.power_fields import DecodeFields
from soc.decoder.power_fieldsn import SignalBitRange
with m.If(~ov): # result is valid (no overflow)
with m.Switch(op.insn_type):
- with m.Case(InternalOp.OP_DIVE):
+ with m.Case(MicrOp.OP_DIVE):
with m.If(op.is_32bit):
with m.If(op.is_signed):
# matches POWER9's divweo behavior
comb += o.eq(quotient_65[0:32].as_unsigned())
with m.Else():
comb += o.eq(quotient_65)
- with m.Case(InternalOp.OP_DIV):
+ with m.Case(MicrOp.OP_DIV):
with m.If(op.is_32bit):
with m.If(op.is_signed):
# matches POWER9's divwo behavior
comb += o.eq(quotient_65[0:32].as_unsigned())
with m.Else():
comb += o.eq(quotient_65)
- with m.Case(InternalOp.OP_MOD):
+ with m.Case(MicrOp.OP_MOD):
with m.If(op.is_32bit):
with m.If(op.is_signed):
# matches POWER9's modsw behavior
from nmutil.pipemodbase import PipeModBase
from soc.fu.div.pipe_data import DIVInputData
from ieee754.part.partsig import PartitionedSignal
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
from soc.decoder.power_fields import DecodeFields
from soc.decoder.power_fieldsn import SignalBitRange
# check for absolute overflow condition (32/64)
comb += self.o.dive_abs_ov64.eq((abs_dend >= abs_dor)
- & (op.insn_type == InternalOp.OP_DIVE))
+ & (op.insn_type == MicrOp.OP_DIVE))
comb += self.o.dive_abs_ov32.eq((abs_dend[0:32] >= abs_dor[0:32])
- & (op.insn_type == InternalOp.OP_DIVE))
+ & (op.insn_type == MicrOp.OP_DIVE))
# set divisor based on 32/64 bit mode (must be absolute)
comb += eq32(op.is_32bit, divisor_o, abs_dor)
with m.Switch(op.insn_type):
# div/mod takes straight (absolute) dividend
- with m.Case(InternalOp.OP_DIV, InternalOp.OP_MOD):
+ with m.Case(MicrOp.OP_DIV, MicrOp.OP_MOD):
comb += eq32(op.is_32bit, dividend_o, abs_dend)
# extended div shifts dividend up
- with m.Case(InternalOp.OP_DIVE):
+ with m.Case(MicrOp.OP_DIVE):
with m.If(op.is_32bit):
comb += dividend_o.eq(abs_dend[0:32] << 32)
with m.Else():
from soc.decoder.isa.caller import ISACaller, special_sprs
from soc.decoder.power_decoder import (create_pdecode)
from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
+from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)
from soc.decoder.selectable_int import SelectableInt
from soc.simulator.program import Program
from soc.decoder.isa.all import ISA
from nmigen.hdl.rec import Record, Layout
-from soc.decoder.power_enums import InternalOp, Function, LDSTMode
+from soc.decoder.power_enums import MicrOp, Function, LDSTMode
class CompLDSTOpSubset(Record):
note: rc / oe is needed (later) for st*cx when it comes to setting OV/SO
"""
def __init__(self, name=None):
- layout = (('insn_type', InternalOp),
+ layout = (('insn_type', MicrOp),
('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
('zero_a', 1),
('rc', Layout((("rc", 1), ("rc_ok", 1)))), # for later
from soc.decoder.isa.caller import special_sprs
from soc.decoder.power_decoder import (create_pdecode)
from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
+from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)
from soc.decoder.selectable_int import SelectableInt
from soc.simulator.program import Program
from soc.decoder.isa.all import ISA
from soc.fu.alu.input_stage import ALUInputStage
from soc.fu.alu.pipe_data import ALUPipeSpec
from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
import unittest
comb += Assert(dut.o.a == a)
with m.If(rec.imm_data.imm_ok &
- ~(rec.insn_type == InternalOp.OP_RLC)):
+ ~(rec.insn_type == MicrOp.OP_RLC)):
comb += Assert(dut.o.b == rec.imm_data.imm)
with m.Else():
comb += Assert(dut.o.b == b)
from soc.fu.logical.main_stage import LogicalMainStage
from soc.fu.alu.pipe_data import ALUPipeSpec
from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
import unittest
# main assertion of arithmetic operations
with m.Switch(rec.insn_type):
- with m.Case(InternalOp.OP_AND):
+ with m.Case(MicrOp.OP_AND):
comb += Assert(o == a & b)
- with m.Case(InternalOp.OP_OR):
+ with m.Case(MicrOp.OP_OR):
comb += Assert(o == a | b)
- with m.Case(InternalOp.OP_XOR):
+ with m.Case(MicrOp.OP_XOR):
comb += Assert(o == a ^ b)
- with m.Case(InternalOp.OP_POPCNT):
+ with m.Case(MicrOp.OP_POPCNT):
with m.If(rec.data_len == 8):
comb += Assert(o == simple_popcount(a, 64))
with m.If(rec.data_len == 4):
slc = slice(i*8, (i+1)*8)
comb += Assert(o[slc] == simple_popcount(a[slc], 8))
- with m.Case(InternalOp.OP_PRTY):
+ with m.Case(MicrOp.OP_PRTY):
with m.If(rec.data_len == 8):
result = 0
for i in range(8):
comb += Assert(o[0:32] == result_low)
comb += Assert(o[32:64] == result_high)
- with m.Case(InternalOp.OP_CNTZ):
+ with m.Case(MicrOp.OP_CNTZ):
XO = dut.fields.FormX.XO[0:-1]
with m.If(rec.is_32bit):
m.submodules.pe32 = pe32 = PriorityEncoder(32)
comb += pe64.i.eq(a[0:64][::-1])
comb += Assert(o == peo64)
- with m.Case(InternalOp.OP_CMPB):
+ with m.Case(MicrOp.OP_CMPB):
for i in range(8):
slc = slice(i*8, (i+1)*8)
with m.If(a[slc] == b[slc]):
with m.Else():
comb += Assert(o[slc] == 0)
- with m.Case(InternalOp.OP_BPERM):
+ with m.Case(MicrOp.OP_BPERM):
# note that this is a copy of the beautifully-documented
# proof_bpermd.py
comb += Assert(o[8:] == 0)
from nmigen.hdl.rec import Record, Layout
-from soc.decoder.power_enums import InternalOp, Function, CryIn
+from soc.decoder.power_enums import MicrOp, Function, CryIn
class CompLogicalOpSubset(Record):
grab subsets.
"""
def __init__(self, name=None):
- layout = (('insn_type', InternalOp),
+ layout = (('insn_type', MicrOp),
('fn_unit', Function),
('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
('rc', Layout((("rc", 1), ("rc_ok", 1)))),
from soc.fu.logical.popcount import Popcount
from soc.fu.logical.pipe_data import LogicalOutputData
from ieee754.part.partsig import PartitionedSignal
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
from soc.decoder.power_fields import DecodeFields
from soc.decoder.power_fieldsn import SignalBitRange
with m.Switch(op.insn_type):
###### AND, OR, XOR #######
- with m.Case(InternalOp.OP_AND):
+ with m.Case(MicrOp.OP_AND):
comb += o.data.eq(a & b)
- with m.Case(InternalOp.OP_OR):
+ with m.Case(MicrOp.OP_OR):
comb += o.data.eq(a | b)
- with m.Case(InternalOp.OP_XOR):
+ with m.Case(MicrOp.OP_XOR):
comb += o.data.eq(a ^ b)
###### cmpb #######
- with m.Case(InternalOp.OP_CMPB):
+ with m.Case(MicrOp.OP_CMPB):
l = []
for i in range(8):
slc = slice(i*8, (i+1)*8)
comb += o.data.eq(Cat(*l))
###### popcount #######
- with m.Case(InternalOp.OP_POPCNT):
+ with m.Case(MicrOp.OP_POPCNT):
comb += popcount.a.eq(a)
comb += popcount.b.eq(b)
comb += popcount.data_len.eq(op.data_len)
comb += o.data.eq(popcount.o)
###### parity #######
- with m.Case(InternalOp.OP_PRTY):
+ with m.Case(MicrOp.OP_PRTY):
# strange instruction which XORs together the LSBs of each byte
par0 = Signal(reset_less=True)
par1 = Signal(reset_less=True)
comb += o[32].eq(par1)
###### cntlz #######
- with m.Case(InternalOp.OP_CNTZ):
+ with m.Case(MicrOp.OP_CNTZ):
XO = self.fields.FormX.XO[0:-1]
count_right = Signal(reset_less=True)
comb += count_right.eq(XO[-1])
comb += o.data.eq(Mux(op.is_32bit, clz.lz-32, clz.lz))
###### bpermd #######
- with m.Case(InternalOp.OP_BPERM):
+ with m.Case(MicrOp.OP_BPERM):
comb += bpermd.rs.eq(a)
comb += bpermd.rb.eq(b)
comb += o.data.eq(bpermd.ra)
from soc.fu.common_output_stage import CommonOutputStage
from soc.fu.logical.pipe_data import LogicalInputData, LogicalOutputData
from ieee754.part.partsig import PartitionedSignal
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
class LogicalOutputStage(CommonOutputStage):
from soc.fu.shift_rot.main_stage import ShiftRotMainStage
from soc.fu.alu.pipe_data import ALUPipeSpec
from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
import unittest
# main assertion of arithmetic operations
with m.Switch(rec.insn_type):
- with m.Case(InternalOp.OP_SHL):
+ with m.Case(MicrOp.OP_SHL):
comb += Assume(ra == 0)
with m.If(rec.is_32bit):
comb += Assert(o[0:32] == ((a << b[0:6]) & 0xffffffff))
comb += Assert(o[32:64] == 0)
with m.Else():
comb += Assert(o == ((a << b[0:7]) & ((1 << 64)-1)))
- with m.Case(InternalOp.OP_SHR):
+ with m.Case(MicrOp.OP_SHR):
comb += Assume(ra == 0)
with m.If(~rec.is_signed):
with m.If(rec.is_32bit):
from nmigen.hdl.rec import Record, Layout
-from soc.decoder.power_enums import InternalOp, Function, CryIn
+from soc.decoder.power_enums import MicrOp, Function, CryIn
class CompMULOpSubset(Record):
grab subsets.
"""
def __init__(self, name=None):
- layout = (('insn_type', InternalOp),
+ layout = (('insn_type', MicrOp),
('fn_unit', Function),
('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
('rc', Layout((("rc", 1), ("rc_ok", 1)))), # Data
from soc.fu.div.pipe_data import DivMulOutputData
from soc.fu.mul.pipe_data import MulOutputData
from ieee754.part.partsig import PartitionedSignal
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
class MulMainStage3(PipeModBase):
# OP_MUL_nnn - select hi32/hi64/lo64 from result
with m.Switch(op.insn_type):
# hi-32 replicated twice
- with m.Case(InternalOp.OP_MUL_H32):
+ with m.Case(MicrOp.OP_MUL_H32):
comb += o.data.eq(Repl(mul_o[32:64], 2))
# hi-64
- with m.Case(InternalOp.OP_MUL_H64):
+ with m.Case(MicrOp.OP_MUL_H64):
comb += o.data.eq(mul_o[64:128])
# lo-64 - overflow
with m.Default():
from soc.decoder.isa.caller import ISACaller, special_sprs
from soc.decoder.power_decoder import (create_pdecode)
from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
+from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)
from soc.decoder.selectable_int import SelectableInt
from soc.simulator.program import Program
from soc.decoder.isa.all import ISA
from soc.fu.shift_rot.main_stage import ShiftRotMainStage
from soc.fu.alu.pipe_data import ALUPipeSpec
from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
import unittest
# main assertion of arithmetic operations
with m.Switch(rec.insn_type):
- with m.Case(InternalOp.OP_SHL):
+ with m.Case(MicrOp.OP_SHL):
comb += Assume(ra == 0)
with m.If(rec.is_32bit):
comb += Assert(o[0:32] == ((a << b[0:6]) & 0xffffffff))
with m.Else():
comb += Assert(o == ((a << b[0:7]) & ((1 << 64)-1)))
- with m.Case(InternalOp.OP_SHR):
+ with m.Case(MicrOp.OP_SHR):
comb += Assume(ra == 0)
with m.If(~rec.is_signed):
with m.If(rec.is_32bit):
with m.Else():
comb += Assert(o == (a_signed >> b[0:7]))
#TODO
- with m.Case(InternalOp.OP_RLC):
+ with m.Case(MicrOp.OP_RLC):
pass
- with m.Case(InternalOp.OP_RLCR):
+ with m.Case(MicrOp.OP_RLCR):
pass
- with m.Case(InternalOp.OP_RLCL):
+ with m.Case(MicrOp.OP_RLCL):
pass
with m.Default():
comb += o_ok.eq(0)
from soc.fu.logical.pipe_data import LogicalOutputData
from soc.fu.shift_rot.pipe_data import ShiftRotInputData
from ieee754.part.partsig import PartitionedSignal
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
from soc.fu.shift_rot.rotator import Rotator
from soc.decoder.power_fields import DecodeFields
# instruction rotate type
mode = Signal(3, reset_less=True)
with m.Switch(op.insn_type):
- with m.Case(InternalOp.OP_SHL): comb += mode.eq(0b000)
- with m.Case(InternalOp.OP_SHR): comb += mode.eq(0b001) # R-shift
- with m.Case(InternalOp.OP_RLC): comb += mode.eq(0b110) # clear LR
- with m.Case(InternalOp.OP_RLCL): comb += mode.eq(0b010) # clear L
- with m.Case(InternalOp.OP_RLCR): comb += mode.eq(0b100) # clear R
+ with m.Case(MicrOp.OP_SHL): comb += mode.eq(0b000)
+ with m.Case(MicrOp.OP_SHR): comb += mode.eq(0b001) # R-shift
+ with m.Case(MicrOp.OP_RLC): comb += mode.eq(0b110) # clear LR
+ with m.Case(MicrOp.OP_RLCL): comb += mode.eq(0b010) # clear L
+ with m.Case(MicrOp.OP_RLCR): comb += mode.eq(0b100) # clear R
with m.Default():
comb += o.ok.eq(0) # otherwise disable
from nmigen.hdl.rec import Record, Layout
-from soc.decoder.power_enums import InternalOp, Function, CryIn
+from soc.decoder.power_enums import MicrOp, Function, CryIn
class CompSROpSubset(Record):
grab subsets.
"""
def __init__(self, name=None):
- layout = (('insn_type', InternalOp),
+ layout = (('insn_type', MicrOp),
('fn_unit', Function),
('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
('rc', Layout((("rc", 1), ("rc_ok", 1)))),
from nmigen import (Module, Signal, Cat)
from nmutil.pipemodbase import PipeModBase
from soc.fu.spr.pipe_data import SPRInputData, SPROutputData
-from soc.decoder.power_enums import InternalOp, SPR, XER_bits
+from soc.decoder.power_enums import MicrOp, SPR, XER_bits
from soc.decoder.power_fields import DecodeFields
from soc.decoder.power_fieldsn import SignalBitRange
# TODO: some #defines for the bits n stuff.
with m.Switch(op.insn_type):
#### MTSPR ####
- with m.Case(InternalOp.OP_MTSPR):
+ with m.Case(MicrOp.OP_MTSPR):
with m.Switch(spr):
# fast SPRs first
with m.Case(SPR.CTR, SPR.LR, SPR.TAR, SPR.SRR0, SPR.SRR1):
# slow SPRs TODO
# move from SPRs
- with m.Case(InternalOp.OP_MFSPR):
+ with m.Case(MicrOp.OP_MFSPR):
comb += o.ok.eq(1)
with m.Switch(spr):
# fast SPRs first
from nmigen.hdl.rec import Record, Layout
-from soc.decoder.power_enums import (InternalOp, Function)
+from soc.decoder.power_enums import (MicrOp, Function)
class CompSPROpSubset(Record):
grab subsets.
"""
def __init__(self, name=None):
- layout = (('insn_type', InternalOp),
+ layout = (('insn_type', MicrOp),
('fn_unit', Function),
('insn', 32),
('is_32bit', 1),
from soc.decoder.isa.caller import ISACaller, special_sprs
from soc.decoder.power_decoder import (create_pdecode)
from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
+from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)
from soc.decoder.selectable_int import SelectableInt
from soc.simulator.program import Program
from soc.decoder.isa.all import ISA
from nmutil.extend import exts
from soc.fu.trap.pipe_data import TrapInputData, TrapOutputData
from soc.fu.branch.main_stage import br_ext
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
from soc.decoder.power_fields import DecodeFields
from soc.decoder.power_fieldsn import SignalBitRange
# TODO: some #defines for the bits n stuff.
with m.Switch(op.insn_type):
#### trap ####
- with m.Case(InternalOp.OP_TRAP):
+ with m.Case(MicrOp.OP_TRAP):
# trap instructions (tw, twi, td, tdi)
with m.If(should_trap):
# generate trap-type program interrupt
comb += srr1_o.data[PI.ILLEG].eq(1)
# move to MSR
- with m.Case(InternalOp.OP_MTMSRD, InternalOp.OP_MTMSR):
+ with m.Case(MicrOp.OP_MTMSRD, MicrOp.OP_MTMSR):
L = self.fields.FormX.L[0:-1] # X-Form field L
# start with copy of msr
comb += msr_o.eq(msr_i)
comb += msr_o.ok.eq(1)
# move from MSR
- with m.Case(InternalOp.OP_MFMSR):
+ with m.Case(MicrOp.OP_MFMSR):
# TODO: some of the bits need zeroing? apparently not
comb += o.data.eq(msr_i)
comb += o.ok.eq(1)
- with m.Case(InternalOp.OP_RFID):
+ with m.Case(MicrOp.OP_RFID):
# XXX f_out.virt_mode <= b_in(MSR.IR) or b_in(MSR.PR);
# XXX f_out.priv_mode <= not b_in(MSR.PR);
comb += msr_o.ok.eq(1)
# OP_SC
- with m.Case(InternalOp.OP_SC):
+ with m.Case(MicrOp.OP_SC):
# TODO: scv must generate illegal instruction. this is
# the decoder's job, not ours, here.
self.trap(m, 0xc00, cia_i+4)
# TODO (later)
- #with m.Case(InternalOp.OP_ADDPCIS):
+ #with m.Case(MicrOp.OP_ADDPCIS):
# pass
comb += self.o.ctx.eq(self.i.ctx)
from soc.decoder.isa.caller import ISACaller, special_sprs
from soc.decoder.power_decoder import (create_pdecode)
from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
+from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)
from soc.decoder.selectable_int import SelectableInt
from soc.simulator.program import Program
from soc.decoder.isa.all import ISA
from nmigen.hdl.rec import Record, Layout
-from soc.decoder.power_enums import (InternalOp, Function)
+from soc.decoder.power_enums import (MicrOp, Function)
class CompTrapOpSubset(Record):
grab subsets.
"""
def __init__(self, name=None):
- layout = (('insn_type', InternalOp),
+ layout = (('insn_type', MicrOp),
('fn_unit', Function),
('insn', 32),
('is_32bit', 1),
from soc.decoder.decode2execute1 import Data
from soc.experiment.l0_cache import TstL0CacheBuffer # test only
from soc.config.test.test_loadstore import TestMemPspec
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
import operator
with m.If(can_run):
with m.Switch(dec2.e.do.insn_type):
# check for ATTN: halt if true
- with m.Case(InternalOp.OP_ATTN):
+ with m.Case(MicrOp.OP_ATTN):
m.d.sync += core_stopped.eq(1)
- with m.Case(InternalOp.OP_NOP):
+ with m.Case(MicrOp.OP_NOP):
sync += counter.eq(2)
comb += self.busy_o.eq(1)
from soc.simple.core import NonProductionCore
from soc.config.test.test_loadstore import TestMemPspec
from soc.config.ifetch import ConfigFetchUnit
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
class TestIssuer(Elaboratable):
with m.If(core.core_terminated_o):
m.next = "IDLE" # back to idle, immediately (OP_ATTN)
with m.Else():
- with m.If(insn_type != InternalOp.OP_NOP):
+ with m.If(insn_type != MicrOp.OP_NOP):
comb += core_ivalid_i.eq(1) # instruction is valid
comb += core_opcode_i.eq(ilatch) # actual opcode
with m.If(self.fast_nia.wen):
from nmigen.test.utils import FHDLTestCase
import unittest
from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_enums import (Function, InternalOp,
+from soc.decoder.power_enums import (Function, MicrOp,
In1Sel, In2Sel, In3Sel,
OutSel, RC, LdstLen, CryIn,
single_bit_flags, Form, SPR,
from nmigen.test.utils import FHDLTestCase
import unittest
from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_enums import (Function, InternalOp,
+from soc.decoder.power_enums import (Function, MicrOp,
In1Sel, In2Sel, In3Sel,
OutSel, RC, LdstLen, CryIn,
single_bit_flags, Form, SPR,
from nmigen.test.utils import FHDLTestCase
import unittest
from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_enums import (Function, InternalOp,
+from soc.decoder.power_enums import (Function, MicrOp,
In1Sel, In2Sel, In3Sel,
OutSel, RC, LdstLen, CryIn,
single_bit_flags, Form, SPR,
from nmigen.test.utils import FHDLTestCase
import unittest
from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_enums import (Function, InternalOp,
+from soc.decoder.power_enums import (Function, MicrOp,
In1Sel, In2Sel, In3Sel,
OutSel, RC, LdstLen, CryIn,
single_bit_flags, Form, SPR,
from nmigen.test.utils import FHDLTestCase
import unittest
from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_enums import (Function, InternalOp,
+from soc.decoder.power_enums import (Function, MicrOp,
In1Sel, In2Sel, In3Sel,
OutSel, RC, LdstLen, CryIn,
single_bit_flags, Form, SPR,
projects / soc.git / commitdiff