| 2022-03-12 |
Luke Kenneth Casso... | add extra pipeline stages to ALU FU to make timing |
tree | commitdiff |
| 2022-02-27 |
Luke Kenneth Casso... | bit_length is 1 more than needed: subtract 1 from XLEN... |
tree | commitdiff |
| 2022-02-27 |
Luke Kenneth Casso... | fix up shift_rot test_pipe_caller to new regspeckls... |
tree | commitdiff |
| 2022-02-27 |
Luke Kenneth Casso... | convert shift_rot pipeline to XLEN=32/64 |
tree | commitdiff |
| 2022-02-27 |
Luke Kenneth Casso... | fix up Logical pipeline to produce HDL with XLEN=32 |
tree | commitdiff |
| 2022-02-27 |
Luke Kenneth Casso... | whoops ALU common output target must be XLEN-bit, |
tree | commitdiff |
| 2022-02-27 |
Luke Kenneth Casso... | set up dummy parent_pspec to pass XLEN=64 in |
tree | commitdiff |
| 2022-02-27 |
Luke Kenneth Casso... | start on converting MUL and DIV pipelines to XLEN |
tree | commitdiff |
| 2022-02-27 |
Luke Kenneth Casso... | convert from public static functions/properties for... |
tree | commitdiff |
| 2022-02-27 |
Luke Kenneth Casso... | fix ALU with XLEN=32, carry and overflow |
tree | commitdiff |
| 2022-02-27 |
Luke Kenneth Casso... | use XLEN in Function Units (starting with ALU) |
tree | commitdiff |
| 2022-02-24 |
Jacob Lifshay | add running instructions |
tree | commitdiff |
| 2022-02-24 |
Jacob Lifshay | add formal proof for shift/rot o.ok |
tree | commitdiff |
| 2022-02-24 |
Jacob Lifshay | clean up code |
tree | commitdiff |
| 2022-02-24 |
Jacob Lifshay | add formal proof for OP_RLCR |
tree | commitdiff |
| 2022-02-24 |
Jacob Lifshay | add formal proof for OP_RLCL |
tree | commitdiff |
| 2022-02-24 |
Jacob Lifshay | add formal proof for OP_RLC |
tree | commitdiff |
| 2022-02-23 |
Luke Kenneth Casso... | forgot to pass cix (cache-inhibited) through to LD... |
tree | commitdiff |
| 2022-02-22 |
Jacob Lifshay | speed up shift/rot formal proof by running stuff in... |
tree | commitdiff |
| 2022-02-21 |
Luke Kenneth Casso... | again reduce combinatorial chains, similar to Trap... |
tree | commitdiff |
| 2022-02-20 |
Luke Kenneth Casso... | same as shiftrot, split out separate pipelines for... |
tree | commitdiff |
| 2022-02-20 |
Luke Kenneth Casso... | nope, it's perfectly fine |
tree | commitdiff |
| 2022-02-20 |
Luke Kenneth Casso... | weird exception, oe not found in the shiftrot input... |
tree | commitdiff |
| 2022-02-20 |
Luke Kenneth Casso... | separate out shiftrot stages due to size of main stage... |
tree | commitdiff |
| 2022-02-18 |
Jacob Lifshay | add grev |
tree | commitdiff |
| 2022-02-13 |
Luke Kenneth Casso... | Revert "remove dummy trap pipeline" |
tree | commitdiff |
| 2022-02-13 |
Luke Kenneth Casso... | Revert "doh" |
tree | commitdiff |
| 2022-01-31 |
Luke Kenneth Casso... | doh |
tree | commitdiff |
| 2022-01-31 |
Luke Kenneth Casso... | remove dummy trap pipeline |
tree | commitdiff |
| 2022-01-28 |
Luke Kenneth Casso... | in LoadStore1 capture the address for misaligned dual... |
tree | commitdiff |
| 2022-01-28 |
Luke Kenneth Casso... | sort out misaligned store in LoadStore1 |
tree | commitdiff |
| 2022-01-27 |
Luke Kenneth Casso... | for second aligned request truncate address to nearest... |
tree | commitdiff |
| 2022-01-25 |
Luke Kenneth Casso... | LDSTException now passing bits of SRR1 around to the... |
tree | commitdiff |
| 2022-01-24 |
Luke Kenneth Casso... | bool test on traptype to |
tree | commitdiff |
| 2022-01-21 |
Luke Kenneth Casso... | skip ilang data in branch test_pipe_caller.py |
tree | commitdiff |
| 2022-01-21 |
Luke Kenneth Casso... | attempting to get compunit and test_pipe_caller unit... |
tree | commitdiff |
| 2022-01-20 |
Luke Kenneth Casso... | whoops MFSPR DEC/TB was reading from FastRegs not StateRegs |
tree | commitdiff |
| 2022-01-19 |
Luke Kenneth Casso... | ISI (0x400) trap is the only one that puts memory-based... |
tree | commitdiff |
| 2022-01-19 |
Luke Kenneth Casso... | move DEC and TB into StateRegs, to make room in FastRegs |
tree | commitdiff |
| 2022-01-18 |
Luke Kenneth Casso... | comments on SRR1 in trap |
tree | commitdiff |
| 2022-01-18 |
Luke Kenneth Casso... | preserve bits of SRR1 on a TRAP (including all interrup... |
tree | commitdiff |
| 2022-01-17 |
Luke Kenneth Casso... | fix hrfid and mtmsrd so that it is identical to microwatt |
tree | commitdiff |
| 2022-01-16 |
Luke Kenneth Casso... | raise interrupt on misaligned atomic LDST |
tree | commitdiff |
| 2022-01-16 |
Luke Kenneth Casso... | pass over store_done correctly from dcache over PortInt... |
tree | commitdiff |
| 2022-01-16 |
Luke Kenneth Casso... | add CR0 to LDSTCompUnit, for reporting if LR/SC store... |
tree | commitdiff |
| 2022-01-15 |
Luke Kenneth Casso... | pass over atomic signals to dcache from loadstore. |
tree | commitdiff |
| 2022-01-15 |
Luke Kenneth Casso... | pass atomic reserve through from PortInterface to DCache |
tree | commitdiff |
| 2022-01-15 |
Luke Kenneth Casso... | add reserve (atomic) signal to LDST data structures... |
tree | commitdiff |
| 2022-01-12 |
Luke Kenneth Casso... | fix issue with priv_mode not being passed correctly... |
tree | commitdiff |
| 2022-01-10 |
Luke Kenneth Casso... | LoadStore1 priv_mode was not being correctly picked... |
tree | commitdiff |
| 2022-01-09 |
Luke Kenneth Casso... | add linux-5.7 unit test which showed a silly error: |
tree | commitdiff |
| 2022-01-08 |
Luke Kenneth Casso... | fix MMU lookup after 2nd request (misaligned) by also... |
tree | commitdiff |
| 2022-01-08 |
Luke Kenneth Casso... | do not clear out ldst request after TLB entry is added |
tree | commitdiff |
| 2022-01-08 |
Luke Kenneth Casso... | add a second LD request to dcache which is merged with... |
tree | commitdiff |
| 2022-01-08 |
Luke Kenneth Casso... | start adding in mis-aligned LD/ST support into LoadStore1 |
tree | commitdiff |
| 2022-01-06 |
Luke Kenneth Casso... | add SECOND_REQ state to loadstore.py, not yet implemented |
tree | commitdiff |
| 2022-01-03 |
Luke Kenneth Casso... | adding an extra option to issuer_verilog.py to be able... |
tree | commitdiff |
| 2021-12-30 |
Luke Kenneth Casso... | rename nia to cia in MMU input record and mmu FSM |
tree | commitdiff |
| 2021-12-28 |
Luke Kenneth Casso... | add misaligned mmu.bin test 5 notes: currently LoadStor... |
tree | commitdiff |
| 2021-12-26 |
Luke Kenneth Casso... | rename addr to raddr in LoadStore1 to avoid conflict... |
tree | commitdiff |
| 2021-12-22 |
Luke Kenneth Casso... | when setting DSISR in LoadStore1 use correct load bit... |
tree | commitdiff |
| 2021-12-22 |
Luke Kenneth Casso... | use correct X-Form L field in OP_MTMSRD |
tree | commitdiff |
| 2021-12-22 |
Luke Kenneth Casso... | check problem state in OP_MTMSRD from original reg... |
tree | commitdiff |
| 2021-12-22 |
Luke Kenneth Casso... | remove unneeded state in LoadStore1 |
tree | commitdiff |
| 2021-12-22 |
Luke Kenneth Casso... | clear instruction fault on exception WAIT_MMU ACK in... |
tree | commitdiff |
| 2021-12-22 |
Luke Kenneth Casso... | clear out instr_fault when exception is thrown |
tree | commitdiff |
| 2021-12-22 |
Luke Kenneth Casso... | clear instruction fault on idle/valid in Loadstore1 |
tree | commitdiff |
| 2021-12-21 |
Luke Kenneth Casso... | for each unit test case in test_issuer_mmu_data_path... |
tree | commitdiff |
| 2021-12-21 |
Luke Kenneth Casso... | test_issuer_mmu_data_path.py needs to use wb_get because of |
tree | commitdiff |
| 2021-12-20 |
Luke Kenneth Casso... | unit tests for SPRs when MMU enabled, |
tree | commitdiff |
| 2021-12-18 |
Luke Kenneth Casso... | forgot to connect up I-Cache to MMU |
tree | commitdiff |
| 2021-12-14 |
Luke Kenneth Casso... | get OP_FETCH_FAILED to respond/return an exception... |
tree | commitdiff |
| 2021-12-14 |
Luke Kenneth Casso... | MMU LOOKUP for fetch failed, priv mode is inversion... |
tree | commitdiff |
| 2021-12-14 |
Luke Kenneth Casso... | link MSR.PR into MMU FSM OP_FETCH_FAILED |
tree | commitdiff |
| 2021-12-13 |
Luke Kenneth Casso... | convert LoadStore1 to new msr.pr/dr/sf |
tree | commitdiff |
| 2021-12-13 |
Luke Kenneth Casso... | add msr to MMU Op Subset record |
tree | commitdiff |
| 2021-12-12 |
Luke Kenneth Casso... | delay MMU LOOKUP done by one clock so that the exceptio... |
tree | commitdiff |
| 2021-12-12 |
Luke Kenneth Casso... | bring MMU exception out where AllFunctionUnits (and... |
tree | commitdiff |
| 2021-12-12 |
Luke Kenneth Casso... | bring exception out from MMU FSM, correct "done" |
tree | commitdiff |
| 2021-12-12 |
Luke Kenneth Casso... | add LDSTException output to MMU |
tree | commitdiff |
| 2021-12-11 |
Luke Kenneth Casso... | connect up I-Cache to FetchUnitInterface |
tree | commitdiff |
| 2021-12-10 |
Jacob Lifshay | add ternlogi to shift_rot formal test |
tree | commitdiff |
| 2021-12-10 |
Jacob Lifshay | fix shift_rot formal proof |
tree | commitdiff |
| 2021-12-09 |
Luke Kenneth Casso... | add I-Cache to FSM local variables |
tree | commitdiff |
| 2021-12-09 |
Luke Kenneth Casso... | include SPR.TB in SPR FU |
tree | commitdiff |
| 2021-12-09 |
Jacob Lifshay | add bitmanip tests |
tree | commitdiff |
| 2021-12-09 |
Jacob Lifshay | add CommonPipeSpec.__getattr__ to forward attributes... |
tree | commitdiff |
| 2021-12-09 |
Jacob Lifshay | add parent_pspec everywhere |
tree | commitdiff |
| 2021-12-09 |
Jacob Lifshay | format code |
tree | commitdiff |
| 2021-12-08 |
Luke Kenneth Casso... | add OP_FETCH_FAILED to MMU Function Unit |
tree | commitdiff |
| 2021-12-08 |
Luke Kenneth Casso... | make LoadStore1 intsr_fault a "captured flag" - strictl... |
tree | commitdiff |
| 2021-12-08 |
Luke Kenneth Casso... | remove MSR and add CIA to MMU Input Record |
tree | commitdiff |
| 2021-12-08 |
Luke Kenneth Casso... | add instr_fault to LoadStore1 FSM |
tree | commitdiff |
| 2021-12-08 |
Jacob Lifshay | add comment about draft instructions |
tree | commitdiff |
| 2021-12-08 |
Jacob Lifshay | account for Mock absurdities |
tree | commitdiff |
| 2021-12-07 |
Luke Kenneth Casso... | set separate "iside" signal in LoadStore1 to not confuse it |
tree | commitdiff |
| 2021-12-07 |
Luke Kenneth Casso... | add in I-Cache into LoadStore1 - presently unused ... |
tree | commitdiff |
| 2021-12-07 |
Jacob Lifshay | make bitmanip operations conditional on pspec.draft_bit... |
tree | commitdiff |
| 2021-12-07 |
Jacob Lifshay | format code |
tree | commitdiff |
| 2021-12-07 |
Jacob Lifshay | move rotator mode assignments as requested by lkcl |
tree | commitdiff |
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