2020-09-23 |
Luke Kenneth Casso... | redo litex SDCard to send out data/cmd o/i/en pins |
tree | commitdiff |
2020-09-23 |
Luke Kenneth Casso... | sort out GPIO with i/o/oe in ls180 |
tree | commitdiff |
2020-09-23 |
Luke Kenneth Casso... | add ls180 pinmap text file |
tree | commitdiff |
2020-09-23 |
Luke Kenneth Casso... | attempt GPIO bi-directional |
tree | commitdiff |
2020-09-23 |
Luke Kenneth Casso... | add I2C master to ls180 |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | add 2 PWMs (quick, easy to do) |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | move dmi_sim to separate module |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | add openocd.cfg experiment |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | create a JTAG platform and connect it up. jtagremote... |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | add jtagremote to litex sim, add new "variant" to core... |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | link litex ls180soc JTAG pads |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | add jtag wishbone and jtag ports to libresoc litex... |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | add sys_rst to Clock Reset Generator |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | add JTAG IOpads and rename rst to sys_rst |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | add similar platforms to ls180.py |
tree | commitdiff |
2020-09-19 |
Luke Kenneth Casso... | add pc_o not connected |
tree | commitdiff |
2020-09-19 |
Luke Kenneth Casso... | set ROM to empty, set SRAM to tiny 0x200, get things... |
tree | commitdiff |
2020-09-19 |
Luke Kenneth Casso... | urk. wishbone slave devices declared incorrectly (I... semi_working_ecp5 |
tree | commitdiff |
2020-09-19 |
Luke Kenneth Casso... | disable internal RAM set SRAM to much smaller |
tree | commitdiff |
2020-09-19 |
Luke Kenneth Casso... | shrink size of SRAM to 8k, move things around |
tree | commitdiff |
2020-09-19 |
Luke Kenneth Casso... | add (disabled) tri-state GPIO |
tree | commitdiff |
2020-09-19 |
Luke Kenneth Casso... | remove the gpio peripheral which was previously hard... |
tree | commitdiff |
2020-09-19 |
Luke Kenneth Casso... | add 3x EINTs to ls180soc |
tree | commitdiff |
2020-09-18 |
Luke Kenneth Casso... | add SPI, sdcard, preliminary GPIO to ls180 pinouts |
tree | commitdiff |
2020-09-18 |
Luke Kenneth Casso... | argh got fed up trying to shoe-horn into sim.py |
tree | commitdiff |
2020-09-17 |
Luke Kenneth Casso... | add versa ecp5 fpga litex build script |
tree | commitdiff |
2020-09-16 |
Luke Kenneth Casso... | make a start on LS180 platform |
tree | commitdiff |
2020-09-16 |
Cole Poirier | add template file/starting point (copy of litex/boards... |
tree | commitdiff |
2020-09-08 |
Luke Kenneth Casso... | bit of a mess, trying to get PowerDecode to not create... |
tree | commitdiff |
2020-09-08 |
Luke Kenneth Casso... | subset columns for PowerDecoder - bit of a mess (done... |
tree | commitdiff |
2020-09-08 |
Luke Kenneth Casso... | create a special subset of Decoder Record for storing... |
tree | commitdiff |
2020-09-06 |
Luke Kenneth Casso... | minor code-munge on SPR-to-FAST mapping |
tree | commitdiff |
2020-09-06 |
Luke Kenneth Casso... | redo generation of microwatt.v from litex |
tree | commitdiff |
2020-09-05 |
Luke Kenneth Casso... | move GPIO IRQ to 15 to match microwatt modifications |
tree | commitdiff |
2020-09-05 |
Luke Kenneth Casso... | XICS addresses in words: divide by 4 |
tree | commitdiff |
2020-09-05 |
Luke Kenneth Casso... | whoops, ICS in litex sim needs to be 0x1000 size region |
tree | commitdiff |
2020-09-05 |
Luke Kenneth Casso... | increase wishbone address width to 29 for xics and... |
tree | commitdiff |
2020-09-05 |
Luke Kenneth Casso... | add simple GPIO wishbone bus to litex sim.py |
tree | commitdiff |
2020-09-04 |
Luke Kenneth Casso... | reduce CSR data width to 8 as an experiment |
tree | commitdiff |
2020-09-04 |
Luke Kenneth Casso... | add UART reserved IRQ @ 0 |
tree | commitdiff |
2020-09-04 |
Luke Kenneth Casso... | add XICS memory regions, shrink litex CSR memmap size... |
tree | commitdiff |
2020-09-04 |
Luke Kenneth Casso... | adding XICS wb slave devices to litex sim |
tree | commitdiff |
2020-09-04 |
Luke Kenneth Casso... | adding option to include XICS external interrupts. |
tree | commitdiff |
2020-09-04 |
Luke Kenneth Casso... | add means to run hello_world.bin under simulation |
tree | commitdiff |
2020-09-03 |
Luke Kenneth Casso... | do more on dcache conversion |
tree | commitdiff |
2020-09-03 |
Luke Kenneth Casso... | testing microwatt 3.bin (2.bin ok) |
tree | commitdiff |
2020-09-02 |
Luke Kenneth Casso... | fix bug in cmpli (and cmplw) |
tree | commitdiff |
2020-09-02 |
Luke Kenneth Casso... | add bc ctr regression test when CTR=0 and CTR=1 |
tree | commitdiff |
2020-08-31 |
Luke Kenneth Casso... | add XER to fastregs and "construct" it in mfspr/mtspr |
tree | commitdiff |
2020-08-30 |
Luke Kenneth Casso... | redo OP_CMP based on microwatt. L=1 had been ignored |
tree | commitdiff |
2020-08-29 |
Luke Kenneth Casso... | break down XER into flags |
tree | commitdiff |
2020-08-29 |
Luke Kenneth Casso... | add XER read via DMI interface to sim.py |
tree | commitdiff |
2020-08-29 |
Luke Kenneth Casso... | investigating CR mtocrf / mfocrf |
tree | commitdiff |
2020-08-25 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
tree | commitdiff |
2020-08-25 |
Luke Kenneth Casso... | add way to capture CR from DMI in litex sim |
tree | commitdiff |
2020-08-24 |
Luke Kenneth Casso... | argh, reading regfile over DMI was overlapped and corru... |
tree | commitdiff |
2020-08-24 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
tree | commitdiff |
2020-08-23 |
Luke Kenneth Casso... | add algebraic ld tests lwax, lwaux |
tree | commitdiff |
2020-08-23 |
Luke Kenneth Casso... | add in DMI "stat" loop which monitors core "stopping" |
tree | commitdiff |
2020-08-23 |
Luke Kenneth Casso... | comment why litex sim mem map is altered |
tree | commitdiff |
2020-08-22 |
Luke Kenneth Casso... | load bios not 1.bin unit test |
tree | commitdiff |
2020-08-22 |
Luke Kenneth Casso... | add means to run microwatt test binaries |
tree | commitdiff |
2020-08-22 |
Luke Kenneth Casso... | investigating litex sdrinit function |
tree | commitdiff |
2020-08-21 |
Luke Kenneth Casso... | testing 64-bit wishbone bus after 32-bit *still* fails... |
tree | commitdiff |
2020-08-21 |
Luke Kenneth Casso... | get litex sim enabled with 32-bit wishbone bus |
tree | commitdiff |
2020-08-17 |
Luke Kenneth Casso... | move Mask to nmutil |
tree | commitdiff |
2020-08-17 |
Luke Kenneth Casso... | use longer memtest in litex sim |
tree | commitdiff |
2020-08-16 |
Luke Kenneth Casso... | attempting to track down bug in litex bios memtest |
tree | commitdiff |
2020-08-16 |
Luke Kenneth Casso... | limit debug reporting in litex sim to range of pc |
tree | commitdiff |
2020-08-15 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
tree | commitdiff |
2020-08-15 |
Luke Kenneth Casso... | thanks to daveshah, added simulation of dram |
tree | commitdiff |
2020-08-05 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2020-08-05 |
Luke Kenneth Casso... | rename ibus/dbus (shorten) |
tree | commitdiff |
2020-08-05 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
tree | commitdiff |
2020-08-05 |
Luke Kenneth Casso... | adding bus data width of 64 in litex sim doesnt work |
tree | commitdiff |
2020-08-04 |
Luke Kenneth Casso... | cycle through INT regs, read and debug in litex sim |
tree | commitdiff |
2020-08-04 |
Luke Kenneth Casso... | add DMI debug interface to libresoc litex sim |
tree | commitdiff |
2020-08-04 |
Luke Kenneth Casso... | single-step and print out PC using DMI in litex sim |
tree | commitdiff |
2020-08-04 |
Luke Kenneth Casso... | get litex sim to kick off a "STEP" via the DMI interfac... |
tree | commitdiff |
2020-08-04 |
Luke Kenneth Casso... | connect up a DMI FSM to litex sim |
tree | commitdiff |
2020-08-04 |
Luke Kenneth Casso... | more remove wildcard imports |
tree | commitdiff |
2020-08-04 |
Luke Kenneth Casso... | do not use wildcard imports |
tree | commitdiff |
2020-08-04 |
Luke Kenneth Casso... | adding litex sim experimentation. |
tree | commitdiff |
2020-07-23 |
Luke Kenneth Casso... | syntax error |
tree | commitdiff |
2020-07-23 |
Luke Kenneth Casso... | support 32-bit mem width setting |
tree | commitdiff |
2020-07-23 |
Luke Kenneth Casso... | try SDRAM SDR |
tree | commitdiff |
2020-07-23 |
Luke Kenneth Casso... | try different MEMTEST_xxx sizes with 64 bit bus width |
tree | commitdiff |
2020-07-22 |
Jacob Lifshay | Merge remote-tracking branch 'origin/master' |
tree | commitdiff |
2020-07-22 |
Luke Kenneth Casso... | re-add CRG (clock reset generator) |
tree | commitdiff |
2020-07-22 |
Luke Kenneth Casso... | add clock domain using snippet taken from random file |
tree | commitdiff |
2020-07-22 |
Luke Kenneth Casso... | cleanup in litex core.py |
tree | commitdiff |
2020-07-22 |
Luke Kenneth Casso... | update comments |
tree | commitdiff |
2020-07-22 |
Luke Kenneth Casso... | add dummy irq set/get |
tree | commitdiff |
2020-07-22 |
Luke Kenneth Casso... | add boot-helper.S etc from microwatt litex core |
tree | commitdiff |
2020-07-22 |
Luke Kenneth Casso... | missed import of Builder, set cpu_type to "None" tempor... |
tree | commitdiff |
2020-07-22 |
Luke Kenneth Casso... | begin converting litex sim to libre-soc |
tree | commitdiff |
2020-07-22 |
Luke Kenneth Casso... | do not use wildcard import |
tree | commitdiff |
2020-07-22 |
Luke Kenneth Casso... | start from vexriscv sim.py from |
tree | commitdiff |
2020-07-22 |
Luke Kenneth Casso... | correct syntax error |
tree | commitdiff |
2020-07-22 |
Luke Kenneth Casso... | first version of litex core (to be submitted upstream... |
tree | commitdiff |
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