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add comments on most likely place to put predicate mask read-firing
[soc.git]
/
src
/
soc
/
simple
/
issuer.py
2020-08-13
Luke Kenneth Casso...
sigh. convert INT regfile to binary addressing
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2020-08-11
Luke Kenneth Casso...
reduce regfile ports by creating separate STATE regfile
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2020-08-11
Luke Kenneth Casso...
reducing regfile port usage by sharing read ports
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2020-08-10
Cole Poirier
Merge branch 'master' of git.libre-soc.org:soc
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2020-08-09
Luke Kenneth Casso...
fix combinatorial loop in ldst compunit
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2020-08-09
Luke Kenneth Casso...
use rising edge detection on st go_i/rel_o
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2020-08-09
Luke Kenneth Casso...
get rid of MSR read combinatorial loop
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2020-08-09
Luke Kenneth Casso...
delay go_st by one cycle, break combinatorial loop
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2020-08-05
Cole Poirier
Merge branch 'master' of git.libre-soc.org:soc
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2020-08-05
Luke Kenneth Casso...
add div FSM as default for test_issuer in verilog and...
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2020-08-04
Luke Kenneth Casso...
read/set pc outside of FSM so that DMI interface can...
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2020-08-04
Luke Kenneth Casso...
whoops must output NIA not PC to debug DMI query in...
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2020-08-04
Luke Kenneth Casso...
add DMI debug interface to libresoc litex sim
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2020-08-03
Luke Kenneth Casso...
add quick demo/test of reading DMI reg 9
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2020-08-03
Luke Kenneth Casso...
pass state (MSR/PC) around between PowerDecode2, DMI...
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2020-08-03
Luke Kenneth Casso...
use new soc.config.state CoreState class in DMI and...
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2020-08-03
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-08-03
Luke Kenneth Casso...
change over to DMI debug start/stop interface
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2020-07-31
Luke Kenneth Casso...
restrict external port list further in test_issuer
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2020-07-30
Luke Kenneth Casso...
core_start/stop/endian were inverted (output)
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2020-07-30
Luke Kenneth Casso...
ha! have to explicitly specify the ports when writing...
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2020-07-29
Luke Kenneth Casso...
bit of a big change: add prefixes "cu_" to all CompUnit...
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2020-07-23
Luke Kenneth Casso...
allow imem to be 64/32 bit wide
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2020-07-22
Luke Kenneth Casso...
missing ports from issuer, when doing verilog
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2020-07-22
Luke Kenneth Casso...
reduce number of FastRegs read ports
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2020-07-21
Luke Kenneth Casso...
add PC (CIA) to PowerDecode2 "state" for passing into...
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2020-07-19
Luke Kenneth Casso...
expose core_stop_i to outside as well
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2020-07-19
Luke Kenneth Casso...
set go_insn_i to non-resetless
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2020-07-19
Luke Kenneth Casso...
update to expose signals at top-level of issuer
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2020-07-18
Luke Kenneth Casso...
add option to generate verilog
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2020-07-14
Luke Kenneth Casso...
add MSR reading to issue FSM
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2020-07-12
Luke Kenneth Casso...
rename InternalOp to MicrOp
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2020-07-12
Luke Kenneth Casso...
exit FSM when termination detected
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2020-07-08
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-07
Luke Kenneth Casso...
sort-of got binary execution test working
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2020-07-07
Luke Kenneth Casso...
code-shuffle on testing to prepare loading large files...
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2020-07-07
Luke Kenneth Casso...
add core start/stop capability, and OP_ATTN support
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2020-07-06
Luke Kenneth Casso...
add mul unit to test_issuer
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2020-07-05
Luke Kenneth Casso...
add slow spr regfile regspec support
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2020-07-02
Luke Kenneth Casso...
allow flexible selection of the types of ALUs
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2020-07-02
Luke Kenneth Casso...
add bare wishbone option to TestIssuer, sort out ports
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2020-07-02
Luke Kenneth Casso...
use single-arg pspec for TestIssuer and Core
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2020-07-01
Luke Kenneth Casso...
add name "test_issuer" to ilang conversion
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2020-06-28
Luke Kenneth Casso...
read from instruction memory using FetchUnitInterface
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2020-06-28
Luke Kenneth Casso...
expand instruction bus width to 64 bit, start on a...
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2020-06-27
Luke Kenneth Casso...
make PortInterface modules consistent with same API
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2020-06-18
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-06-18
Luke Kenneth Casso...
got loop example operational by noting when PC fastreg...
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2020-06-18
Luke Kenneth Casso...
slightly hacky way to keep an eye on the PC
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2020-06-17
Luke Kenneth Casso...
split out TestIssuer into separate module
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