projects / soc.git / history
? search:
summary | shortlog | log | commit | commitdiff | tree
first ⋅ prev ⋅ next
finished remaining hdl items
[soc.git] / src / soc / simple /
2021-09-09 klehmanfinished remaining hdl items tree | commitdiff
2021-09-09 klehmanHDL int reg added tree | commitdiff
2021-09-09 klehmanmore sim class registers add tree | commitdiff
2021-09-08 Cesar StraussMonitor exceptions, re-decoding the instruction in... tree | commitdiff
2021-09-08 klehmaninitial commit of sim state class tree | commitdiff
2021-09-08 Cesar StraussMonitor the exception input to PowerDecoder2 tree | commitdiff
2021-09-07 Luke Kenneth Casso... fun fixing of get_core_hdl_regs, "yield from" tree | commitdiff
2021-09-07 Luke Kenneth Casso... move functions to above where they are called tree | commitdiff
2021-09-07 klehmanbreakout of register collection and compare tree | commitdiff
2021-09-07 Cesar StraussFix typo. tree | commitdiff
2021-09-07 Luke Kenneth Casso... add TODO code-comments tree | commitdiff
2021-09-07 Luke Kenneth Casso... whitespace, add bug ref number to test API tree | commitdiff
2021-08-29 Luke Kenneth Casso... unnecessary signal rename ivalid_i to ii_valid (reverting) tree | commitdiff
2021-08-24 Luke Kenneth Casso... replace data_o with o_data and data_i with i_data as... tree | commitdiff
2021-08-24 Luke Kenneth Casso... big rename, global/search/replace of ready_o with o_rea... tree | commitdiff
2021-08-17 Cesar StraussEnable LD/ST exception test case tree | commitdiff
2021-08-16 Cesar StraussAdjust PortInterface traces according to MMU option tree | commitdiff
2021-08-16 Tobias Platenadd WIP DCBZTestCase tree | commitdiff
2021-08-01 Jonathan Neuschäferimport setup_i_memory from soc.simple.test.test_runner tree | commitdiff
2021-08-01 Jonathan Neuschäfersoc.simple.test: Rename setup_test_memory to avoid... tree | commitdiff
2021-07-24 Tobias Platenadd test_issuer_dcache.py tree | commitdiff
2021-07-15 Luke Kenneth Casso... update TestRunner, SVSTATE is now a class that inherits... tree | commitdiff
2021-07-14 Luke Kenneth Casso... update SVSTATE to 64 bit length (fortunately very easy) tree | commitdiff
2021-07-12 Luke Kenneth Casso... use standard create_pdecode in TestRunner tree | commitdiff
2021-07-12 Luke Kenneth Casso... use default decoder, do not pass one in. tree | commitdiff
2021-07-11 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org... tree | commitdiff
2021-07-10 Cesar StraussShow some usage of PortInterface in action tree | commitdiff
2021-06-24 Luke Kenneth Casso... propagate new use_svp64_ldst_dec mode through TestCore... tree | commitdiff
2021-06-24 Luke Kenneth Casso... add an explicit PowerDecoder.is_svp64_mode flag to... tree | commitdiff
2021-06-09 Luke Kenneth Casso... disconnect pll clock, connected in peripheral interconnect tree | commitdiff
2021-06-09 Luke Kenneth Casso... add in/out of ref_clk and pllclk_clk when PLL enabled tree | commitdiff
2021-06-03 Luke Kenneth Casso... comment out domains that have already been created tree | commitdiff
2021-06-03 Luke Kenneth Casso... no, do not assign clock to clock! tree | commitdiff
2021-06-03 Luke Kenneth Casso... sort out PLL domains but bypass PLL due to lack of... tree | commitdiff
2021-06-03 Luke Kenneth Casso... use DomainRenamer on all sub-components of TestIssuer tree | commitdiff
2021-06-03 Luke Kenneth Casso... make core_rst a member of TestIssuerInternal tree | commitdiff
2021-05-27 Luke Kenneth Casso... adjust PLL connections looking for coriolis2 issue tree | commitdiff
2021-05-26 Luke Kenneth Casso... arse. PLL test_issuer clk_sel_i accidentally only 1... tree | commitdiff
2021-05-26 Luke Kenneth Casso... remove err feature from sram4k wb tree | commitdiff
2021-05-26 Luke Kenneth Casso... rename PLL signals tree | commitdiff
2021-05-24 Luke Kenneth Casso... match up PLL names tree | commitdiff
2021-05-22 Cesar StraussMove the reset code outside of the sub-test tree | commitdiff
2021-05-22 Luke Kenneth Casso... update PLL to use Instance tree | commitdiff
2021-05-13 Luke Kenneth Casso... update comments in issuer.py regarding a 4th FSM tree | commitdiff
2021-05-12 Luke Kenneth Casso... bit of a hack to get test_mmu_dcache_pi.py operational. tree | commitdiff
2021-05-10 Luke Kenneth Casso... add block for MMU activation to LoadStore1 tree | commitdiff
2021-05-09 Luke Kenneth Casso... add comments in LoadStore1 tree | commitdiff
2021-05-09 Luke Kenneth Casso... add comment about LD/ST exception needs copying into... tree | commitdiff
2021-05-09 Luke Kenneth Casso... run LD/ST Exception test case for MMU tree | commitdiff
2021-05-07 Luke Kenneth Casso... how we managed to get this far without noticing that... tree | commitdiff
2021-05-07 Luke Kenneth Casso... whoops setup of core.sv_pred_sm/dm not indented and... tree | commitdiff
2021-05-06 Luke Kenneth Casso... whoops disabled tests agaaaaain tree | commitdiff
2021-05-06 Luke Kenneth Casso... pass relevant predicate mask bits through to Decoders... tree | commitdiff
2021-05-06 Luke Kenneth Casso... add in predicate mask bit detection when zeroing is... tree | commitdiff
2021-05-06 Luke Kenneth Casso... pass SVP64 ReMap field through to core and then on... tree | commitdiff
2021-05-06 Luke Kenneth Casso... moved exts* SVP64 unit tests to a different location tree | commitdiff
2021-05-05 Luke Kenneth Casso... whoops wrong signal name, set exc_happened tree | commitdiff
2021-05-04 Luke Kenneth Casso... whoops disabled some test_issuer group tests tree | commitdiff
2021-05-04 Luke Kenneth Casso... new fast3 needs to be remapped to fast1 port in "reduce... tree | commitdiff
2021-05-04 Luke Kenneth Casso... add TODO comments and cross-reference to bug tree | commitdiff
2021-05-04 Luke Kenneth Casso... note a way to see if an exception happened, in TestIssuer tree | commitdiff
2021-05-04 Luke Kenneth Casso... code-comments for LDSTCompUnit tree | commitdiff
2021-05-01 Luke Kenneth Casso... enable issuer_verilog.py to generate new MMU/DCache... tree | commitdiff
2021-05-01 Luke Kenneth Casso... send a DMI RESET at the end of the test. tree | commitdiff
2021-05-01 Luke Kenneth Casso... store data in microwatt dcache goes in one cycle AFTER... tree | commitdiff
2021-05-01 Luke Kenneth Casso... add LD/ST cases to MMU, which should all still work tree | commitdiff
2021-05-01 Luke Kenneth Casso... add MMUTestCaseROM tree | commitdiff
2021-05-01 Luke Kenneth Casso... use new AllFunctionUnits.get_fu function tree | commitdiff
2021-05-01 Luke Kenneth Casso... use SPRreduced to match PowerDecoder2 tree | commitdiff
2021-04-30 Luke Kenneth Casso... add a TestSRAM variant of LoadStore1, for being able... tree | commitdiff
2021-04-30 Luke Kenneth Casso... add basic test_issuer_mmu.py tree | commitdiff
2021-04-30 Luke Kenneth Casso... add option to use new mmu_cache_wb ConfigMemoryPortInte... tree | commitdiff
2021-04-30 Luke Kenneth Casso... https://bugs.libre-soc.org/show_bug.cgi?id=635 tree | commitdiff
2021-04-30 Luke Kenneth Casso... better reporting on gpr comparisons tree | commitdiff
2021-04-30 Luke Kenneth Casso... set up LoadStore1 in ConfigMemoryPortInterface and... tree | commitdiff
2021-04-25 Cesar StraussShift-out skipped mask bits for both crpred and intpred tree | commitdiff
2021-04-24 Luke Kenneth Casso... whitespace tree | commitdiff
2021-04-23 Luke Kenneth Casso... add comments on TestIssuer TestRunner tree | commitdiff
2021-04-23 Luke Kenneth Casso... comment tests back in tree | commitdiff
2021-04-23 Luke Kenneth Casso... error in setting fast regs test values tree | commitdiff
2021-04-23 Luke Kenneth Casso... import from openpower.tests tree | commitdiff
2021-04-23 Luke Kenneth Casso... use openpower.test.common tree | commitdiff
2021-04-23 Luke Kenneth Casso... move more files to openpower-isa tree | commitdiff
2021-04-23 Luke Kenneth Casso... more openpower-isa conversion tree | commitdiff
2021-04-23 Luke Kenneth Casso... correct migration of openpower-isa tree | commitdiff
2021-04-23 Luke Kenneth Casso... move over to from openpower imports tree | commitdiff
2021-04-22 Cesar StraussImplement CR predication tree | commitdiff
2021-04-21 Cesar StraussCR sub-fields are stored in MSB0 order tree | commitdiff
2021-04-21 Tobias Platentestcase: pass PRTBL to mmu tree | commitdiff
2021-04-21 Cesar StraussFix sense of "invert" signal tree | commitdiff
2021-04-20 Luke Kenneth Casso... add enable MMU option to issuer_verilog.py tree | commitdiff
2021-04-18 Luke Kenneth Casso... create signal on test_issuer which gives PLL clk_sel_i... tree | commitdiff
2021-04-18 Luke Kenneth Casso... rename PLL pins to match LIP6.fr PLL tree | commitdiff
2021-04-18 Luke Kenneth Casso... core_stopped_i unused: remove tree | commitdiff
2021-04-17 Cesar StraussImplement 1<<r3 directly by a shift tree | commitdiff
2021-04-10 Cesar StraussImplement 1<<r3 predicate mode tree | commitdiff
2021-04-09 Luke Kenneth Casso... test firmware upload program needed to branch back... tree | commitdiff
2021-04-08 Luke Kenneth Casso... sort out pc reset when DMI interface requests reset tree | commitdiff
2021-04-06 Cesar StraussMake the VL loop reentrant in HDL tree | commitdiff
2021-04-03 Cesar StraussReminder for a possible hardware optimization tree | commitdiff
next