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whoops, using variable RegStage0 in dcache stage_0, should not use sync
[soc.git] / src /
2021-12-26 Luke Kenneth Casso... whoops, using variable RegStage0 in dcache stage_0... tree | commitdiff
2021-12-26 Luke Kenneth Casso... missed reset of d_valid in dcache.py and missed that its tree | commitdiff
2021-12-26 Luke Kenneth Casso... rename addr to raddr in LoadStore1 to avoid conflict... tree | commitdiff
2021-12-25 Luke Kenneth Casso... add mmu.bin test2 to much simpler test_loadstore1.py tree | commitdiff
2021-12-25 Luke Kenneth Casso... move msr in test_loadstore1.py outside of conditional... tree | commitdiff
2021-12-25 Luke Kenneth Casso... whitespace tree | commitdiff
2021-12-25 Luke Kenneth Casso... move microwatt mmu.bin test 3 page table to test pageta... tree | commitdiff
2021-12-25 Luke Kenneth Casso... wait for MMU "done" when setting PRTBL and PIDR tree | commitdiff
2021-12-25 Luke Kenneth Casso... add microwatt mmu.bin regression test test_mmu_3 tree | commitdiff
2021-12-24 Luke Kenneth Casso... enable instruction redirect in mmu ifetch test tree | commitdiff
2021-12-23 Luke Kenneth Casso... somehow managed to miss out setting r1.forward_valid1... tree | commitdiff
2021-12-23 Luke Kenneth Casso... uniquify names in dcache.py tree | commitdiff
2021-12-23 Luke Kenneth Casso... allow MSR reset to default to a value set by issuer_ver... tree | commitdiff
2021-12-23 Luke Kenneth Casso... pass in msr_reset to issuer_verilog.py tree | commitdiff
2021-12-23 Luke Kenneth Casso... add ability to set the reset values of RegFileArray tree | commitdiff
2021-12-23 Cesar StraussRemove extra wait on core_stop_o at end of Execute. tree | commitdiff
2021-12-23 Cesar StraussRe-enable core stopped signal when stopped. tree | commitdiff
2021-12-22 Luke Kenneth Casso... only use a single variable for ack adjusting in dcache.py tree | commitdiff
2021-12-22 Luke Kenneth Casso... fix issues with running core in DMI "stopped" status... tree | commitdiff
2021-12-22 Luke Kenneth Casso... when setting DSISR in LoadStore1 use correct load bit... tree | commitdiff
2021-12-22 Luke Kenneth Casso... use correct X-Form L field in OP_MTMSRD tree | commitdiff
2021-12-22 Luke Kenneth Casso... check problem state in OP_MTMSRD from original reg... tree | commitdiff
2021-12-22 Luke Kenneth Casso... whoops, use MSR.IR for I-Cache fetch! tree | commitdiff
2021-12-22 Luke Kenneth Casso... remove unneeded state in LoadStore1 tree | commitdiff
2021-12-22 Luke Kenneth Casso... clear instruction fault on exception WAIT_MMU ACK in... tree | commitdiff
2021-12-22 Luke Kenneth Casso... clear out instr_fault when exception is thrown tree | commitdiff
2021-12-22 Luke Kenneth Casso... clear instruction fault on idle/valid in Loadstore1 tree | commitdiff
2021-12-22 Luke Kenneth Casso... ooo far too late at night to be doing this tree | commitdiff
2021-12-22 Luke Kenneth Casso... whoops use C not Const tree | commitdiff
2021-12-22 Luke Kenneth Casso... whoops use C not Const tree | commitdiff
2021-12-22 Luke Kenneth Casso... remove bus_ack (found bug in Simulation, sorted) tree | commitdiff
2021-12-22 Luke Kenneth Casso... bug in mmu setting radix tree size with one extra bit tree | commitdiff
2021-12-21 Luke Kenneth Casso... continue to assert PC in FetchFSM if needed tree | commitdiff
2021-12-21 Luke Kenneth Casso... enable I-Cache wishbone memory type in issuer_verilog... tree | commitdiff
2021-12-21 Luke Kenneth Casso... whoops issuer_verilog.py enabling mmu has to pass micro... tree | commitdiff
2021-12-21 Luke Kenneth Casso... for each unit test case in test_issuer_mmu_data_path... tree | commitdiff
2021-12-21 Luke Kenneth Casso... test_issuer_mmu_data_path.py needs to use wb_get because of tree | commitdiff
2021-12-21 Luke Kenneth Casso... mmu code-comments tree | commitdiff
2021-12-21 Luke Kenneth Casso... comments tree | commitdiff
2021-12-21 Luke Kenneth Casso... use prtbl in proc_tbl_wait in mmu tree | commitdiff
2021-12-21 Luke Kenneth Casso... mmu.py comments tree | commitdiff
2021-12-20 Luke Kenneth Casso... set up DAR correctly in unit tests, added set_ldst_spr... tree | commitdiff
2021-12-20 Luke Kenneth Casso... unit tests for SPRs when MMU enabled, tree | commitdiff
2021-12-20 Luke Kenneth Casso... more code-comments tree | commitdiff
2021-12-20 Luke Kenneth Casso... code-comments in MMU tree | commitdiff
2021-12-20 Luke Kenneth Casso... prefer not to invert when doing if/else. tree | commitdiff
2021-12-20 Luke Kenneth Casso... more code-comments tree | commitdiff
2021-12-20 Luke Kenneth Casso... add RTPDE - Radit Tree Page Directory Entry - Record... tree | commitdiff
2021-12-20 Luke Kenneth Casso... add (and ues) PRTBL Record in MMU tree | commitdiff
2021-12-20 Luke Kenneth Casso... create PGTBL Record and use it in MMU page_table_idle tree | commitdiff
2021-12-19 Luke Kenneth Casso... add hard stop address in ifetch unit test, bit of a... tree | commitdiff
2021-12-19 Luke Kenneth Casso... set terminate if core terminate requested tree | commitdiff
2021-12-19 Luke Kenneth Casso... code-comments tree | commitdiff
2021-12-19 Luke Kenneth Casso... add DMI STOPADDR register and use it in HDLRunner to... tree | commitdiff
2021-12-19 Luke Kenneth Casso... break out when core is stopped in HDLRunner tree | commitdiff
2021-12-18 Luke Kenneth Casso... add link to XICS bugreport tree | commitdiff
2021-12-18 Luke Kenneth Casso... sort out reset signalling after tracking down Simulatio... tree | commitdiff
2021-12-18 Luke Kenneth Casso... add icache/dcache/mmu unit test for TestIssuer tree | commitdiff
2021-12-18 Luke Kenneth Casso... get instructions to re-run in issuer after I-Cache... tree | commitdiff
2021-12-18 Luke Kenneth Casso... forgot to connect up I-Cache to MMU tree | commitdiff
2021-12-18 Luke Kenneth Casso... move connection of bus.stall in icache.py, tree | commitdiff
2021-12-18 Luke Kenneth Casso... tidyup tree | commitdiff
2021-12-18 Luke Kenneth Casso... tlb_req_index is TLB_BITS long not TLB_SIZE tree | commitdiff
2021-12-16 Luke Kenneth Casso... whoops, a Simulation bug, dcache bus ack Signal needed... tree | commitdiff
2021-12-16 Luke Kenneth Casso... give names to MMU records tree | commitdiff
2021-12-16 Luke Kenneth Casso... set_mmu_spr was using the slow-SPR index for the regfile tree | commitdiff
2021-12-16 Luke Kenneth Casso... whoops remove duplicate code (cut/paste error) no harm... tree | commitdiff
2021-12-15 Luke Kenneth Casso... remove more unneeded code tree | commitdiff
2021-12-15 Luke Kenneth Casso... read MSR.PR and MSR.DR and update ICache priv/virt... tree | commitdiff
2021-12-15 Luke Kenneth Casso... remove more of SVP64 from TestIssuerInternalInOrder tree | commitdiff
2021-12-15 Luke Kenneth Casso... remove update of pc, msr and svstate from TestIssuerInOrder tree | commitdiff
2021-12-15 Luke Kenneth Casso... move update of pc, msr and svstate into TestIssuerBase tree | commitdiff
2021-12-15 Luke Kenneth Casso... comment-out TestIssuerInternalInorder for now tree | commitdiff
2021-12-15 Luke Kenneth Casso... move alternative TestIssuerInternalInOrder to new file tree | commitdiff
2021-12-15 Luke Kenneth Casso... split out common elaboratable code from TestIssuer, tree | commitdiff
2021-12-15 Luke Kenneth Casso... big split-out of common functions in TestIssuer to... tree | commitdiff
2021-12-15 Luke Kenneth Casso... simplifying / tidyup of TestIssuer to get CoreState tree | commitdiff
2021-12-15 Luke Kenneth Casso... sort out MSR, read/write in same way as PC/SVSTATE... tree | commitdiff
2021-12-15 Luke Kenneth Casso... whoops accidentally commented out setup of instructions tree | commitdiff
2021-12-15 Luke Kenneth Casso... get fetch_failed working with no MMU tree | commitdiff
2021-12-14 Tobias Platentest_loadstore1.py: test_loadstore1_ifetch_multi now... tree | commitdiff
2021-12-14 Luke Kenneth Casso... trying to get TestIssuer FSM to respond correctly to... tree | commitdiff
2021-12-14 Luke Kenneth Casso... get OP_FETCH_FAILED to respond/return an exception... tree | commitdiff
2021-12-14 Luke Kenneth Casso... update wb_get memory with instructions if required tree | commitdiff
2021-12-14 Tobias Platenfix test_loadstore1_ifetch_multi() in test_loadstore1.py tree | commitdiff
2021-12-14 Tobias Platenwip test case for virtual address fetch using fetch... tree | commitdiff
2021-12-14 Tobias Platenfix test_loadstore1_ifetch_multi() tree | commitdiff
2021-12-14 Luke Kenneth Casso... MMU LOOKUP for fetch failed, priv mode is inversion... tree | commitdiff
2021-12-14 Luke Kenneth Casso... link MSR.PR into MMU FSM OP_FETCH_FAILED tree | commitdiff
2021-12-13 Luke Kenneth Casso... request a flush of icache to clear the instruction... tree | commitdiff
2021-12-13 Tobias Platentry to get multi test running tree | commitdiff
2021-12-13 Tobias Platencomments about test_loadstore1_ifetch() tree | commitdiff
2021-12-13 Luke Kenneth Casso... fix test_loadstore1.py with MSR=PR/DR tree | commitdiff
2021-12-13 Luke Kenneth Casso... set pr=0 because privileged mode is pr=0 not pr=1 tree | commitdiff
2021-12-13 Luke Kenneth Casso... add in missing MSRSpec import tree | commitdiff
2021-12-13 Luke Kenneth Casso... commented-out code tree | commitdiff
2021-12-13 Tobias Platenupdate MMU PortInterface Test (misalign) tree | commitdiff
2021-12-13 Tobias Platencleanup test_ldst_pi.py tree | commitdiff
2021-12-13 Tobias Platenupdate old TestMicrowattMemoryPortInterface tree | commitdiff
2021-12-13 Tobias Platenreplace msr_pr with msr tree | commitdiff
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