| 2021-11-19 |
Luke Kenneth Casso... | code tidyup / comments, and use defaultdict |
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| 2021-11-19 |
Luke Kenneth Casso... | create lists of latches in each FU, to record the read... |
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| 2021-11-18 |
Luke Kenneth Casso... | remove combinatorial loop in core instruction conflict... |
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| 2021-11-18 |
Luke Kenneth Casso... | experimenting with overlapping instructions, bit of... |
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| 2021-11-18 |
Luke Kenneth Casso... | set up core processing FSM, which captures data if... |
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| 2021-11-18 |
Luke Kenneth Casso... | set up a temporary copy of CoreInput |
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| 2021-11-18 |
Luke Kenneth Casso... | experiment allowing overlap (activated with --allow... |
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| 2021-11-17 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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| 2021-11-17 |
Luke Kenneth Casso... | reading of regfile bitvector added, which activates... |
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| 2021-11-17 |
Luke Kenneth Casso... | detect the case in Core bitvector when the Function... |
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| 2021-11-17 |
Luke Kenneth Casso... | missing optional check on make_hazard_vecs |
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| 2021-11-17 |
Luke Kenneth Casso... | move core hazard set/clear to separate function, for... |
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| 2021-11-17 |
Luke Kenneth Casso... | whoops context-indentation by mistake (no harm done... |
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| 2021-11-16 |
Luke Kenneth Casso... | print out regfile unary status, bit of name-cleanup |
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| 2021-11-16 |
Luke Kenneth Casso... | use a virtual regfile port for the hazard bitvectors |
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| 2021-11-16 |
Luke Kenneth Casso... | create set/get ports for bitvectors |
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| 2021-11-16 |
Luke Kenneth Casso... | capture write port (wrflag) in byregfiles_spec for... |
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| 2021-11-16 |
Luke Kenneth Casso... | rename regports for bitvectors so that |
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| 2021-11-16 |
Luke Kenneth Casso... | starting to get write-clear of hazard vectors operating |
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| 2021-11-13 |
Luke Kenneth Casso... | start adding hazard vector setting in core (unfinished) |
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| 2021-11-11 |
Luke Kenneth Casso... | debug prints |
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| 2021-11-11 |
Luke Kenneth Casso... | fix regfile port names for "fast" port access (regreduc... |
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| 2021-11-11 |
Luke Kenneth Casso... | code-comments |
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| 2021-11-11 |
Luke Kenneth Casso... | split out core input/output into separate file core_data.py |
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| 2021-11-11 |
Luke Kenneth Casso... | enable hazard vecs in core |
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| 2021-11-10 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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| 2021-11-10 |
Luke Kenneth Casso... | make core busy_o part of the CoreOutput data structure |
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| 2021-11-10 |
Luke Kenneth Casso... | add a "fu_found" signal to core, which allows for an... |
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| 2021-11-09 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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| 2021-11-09 |
Luke Kenneth Casso... | add core instruction-issue PriorityPickers |
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| 2021-11-09 |
Luke Kenneth Casso... | comments |
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| 2021-11-09 |
Luke Kenneth Casso... | core.py: create a dictionary of lists of Function Units... |
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| 2021-11-09 |
Luke Kenneth Casso... | create function core conect_satellite_decoders |
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| 2021-11-08 |
Luke Kenneth Casso... | shorter way of getting FU busy signals |
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| 2021-11-08 |
Luke Kenneth Casso... | MultiCompUnit fixed to not need rdmask to be sustained... |
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| 2021-11-08 |
Luke Kenneth Casso... | code comments |
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| 2021-11-08 |
Luke Kenneth Casso... | comments |
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| 2021-11-08 |
Luke Kenneth Casso... | remove issue_i from core, use i_valid instead to decide... |
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| 2021-11-08 |
Luke Kenneth Casso... | move "exception happened" detection from TestIssuer... |
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| 2021-11-08 |
Luke Kenneth Casso... | use p.i_valid in core instead of explicit signal ivalid_i |
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| 2021-11-08 |
Luke Kenneth Casso... | use Pipeline API o_ready instead of explicit core busy_... |
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| 2021-11-08 |
Luke Kenneth Casso... | convert core.py to Pipeline API, deriving from ControlBase |
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| 2021-11-08 |
Luke Kenneth Casso... | move simple core input and output data to in/out data... |
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| 2021-11-04 |
Luke Kenneth Casso... | add name to write pick on core |
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| 2021-11-01 |
Luke Kenneth Casso... | code comments for core |
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| 2021-08-29 |
Luke Kenneth Casso... | unnecessary signal rename ivalid_i to ii_valid (reverting) |
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| 2021-08-24 |
Luke Kenneth Casso... | replace data_o with o_data and data_i with i_data as... |
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| 2021-08-24 |
Luke Kenneth Casso... | big rename, global/search/replace of ready_o with o_rea... |
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| 2021-06-24 |
Luke Kenneth Casso... | propagate new use_svp64_ldst_dec mode through TestCore... |
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| 2021-06-24 |
Luke Kenneth Casso... | add an explicit PowerDecoder.is_svp64_mode flag to... |
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| 2021-05-06 |
Luke Kenneth Casso... | add in predicate mask bit detection when zeroing is... |
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| 2021-05-06 |
Luke Kenneth Casso... | pass SVP64 ReMap field through to core and then on... |
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| 2021-05-04 |
Luke Kenneth Casso... | new fast3 needs to be remapped to fast1 port in "reduce... |
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| 2021-04-30 |
Luke Kenneth Casso... | add a TestSRAM variant of LoadStore1, for being able... |
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| 2021-04-30 |
Luke Kenneth Casso... | set up LoadStore1 in ConfigMemoryPortInterface and... |
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| 2021-04-23 |
Luke Kenneth Casso... | move over to from openpower imports |
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| 2021-04-18 |
Luke Kenneth Casso... | core_stopped_i unused: remove |
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| 2021-03-30 |
Alain D D Williams | Merge branch 'master' of git.libre-soc.org:soc |
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| 2021-03-28 |
Luke Kenneth Casso... | svp64-enable passed through to PowerDecoderSubsets... |
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| 2021-03-28 |
Luke Kenneth Casso... | add option to reduce number of regfile ports (get DFFs... |
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| 2021-03-28 |
Luke Kenneth Casso... | reduce number of regfile ports |
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| 2021-03-28 |
Luke Kenneth Casso... | reduce regfile port usage on non-svp64 |
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| 2021-03-11 |
Luke Kenneth Casso... | add link of RA_OR_ZERO SVP64 detection |
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| 2021-02-04 |
Tobias Platen | pass SPR MicroOp to MMU function unit |
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| 2021-01-16 |
Tobias Platen | move microwatt_mmu bool variable to pspec |
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| 2021-01-15 |
Tobias Platen | add microwatt_mmu boolean variable to core and compunits |
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| 2020-10-15 |
Luke Kenneth Casso... | sorting out missing clock somewhere |
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| 2020-10-07 |
Luke Kenneth Casso... | reorder / reorganise reset signals slightly |
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| 2020-10-06 |
Luke Kenneth Casso... | skip Decode2ToOperand from PowerDecodeSubset |
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| 2020-09-28 |
Luke Kenneth Casso... | missing pspec |
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| 2020-09-28 |
Luke Kenneth Casso... | add "nocore" option to build verilog |
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| 2020-09-22 |
Luke Kenneth Casso... | add MMU (commented out) |
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| 2020-09-08 |
Luke Kenneth Casso... | create a special subset of Decoder Record for storing... |
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| 2020-09-08 |
Luke Kenneth Casso... | give Decode2Execute1Type in core a name |
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| 2020-09-08 |
Luke Kenneth Casso... | pass in CoreState to PowerDecoder rather than eq a... |
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| 2020-09-07 |
Luke Kenneth Casso... | use PowerDecoderSubsets for FUs, except for TRAP which... |
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| 2020-09-07 |
Luke Kenneth Casso... | add per-FU PowerDecoders. should now be subsettable |
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| 2020-09-05 |
Luke Kenneth Casso... | connect XICS core irq to Decode2 eint |
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| 2020-09-04 |
Luke Kenneth Casso... | adding option to include XICS external interrupts. |
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| 2020-08-15 |
Luke Kenneth Casso... | rather big change to interaction between regfile and... |
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| 2020-08-14 |
Luke Kenneth Casso... | move instruction decoder out of core |
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| 2020-08-14 |
Luke Kenneth Casso... | move regspec / rdflag decoding functions out of PowerDe... |
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| 2020-08-14 |
Luke Kenneth Casso... | put multi-ports back (for read) on int and fast regfiles |
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| 2020-08-13 |
Luke Kenneth Casso... | sync on read of regfile ports |
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| 2020-08-13 |
Luke Kenneth Casso... | sigh. convert INT regfile to binary addressing |
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| 2020-08-11 |
Luke Kenneth Casso... | sigh, remove yet another int regfile read port |
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| 2020-08-11 |
Luke Kenneth Casso... | massive reduction in gate count by using alternative... |
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| 2020-08-11 |
Luke Kenneth Casso... | reduce regfile port usage for INT and FAST |
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| 2020-08-11 |
Luke Kenneth Casso... | prepare write ports to be shared |
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| 2020-08-11 |
Luke Kenneth Casso... | move write regfile picker creation to new function |
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| 2020-08-11 |
Luke Kenneth Casso... | reducing regfile port usage by sharing read ports |
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| 2020-08-10 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
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| 2020-08-09 |
Luke Kenneth Casso... | write pulse in issuer |
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| 2020-08-04 |
Luke Kenneth Casso... | allow instruction to run if initiated whilst "stopped... |
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| 2020-08-03 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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| 2020-08-03 |
Luke Kenneth Casso... | change over to DMI debug start/stop interface |
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| 2020-07-29 |
Luke Kenneth Casso... | bit of a big change: add prefixes "cu_" to all CompUnit... |
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| 2020-07-23 |
Luke Kenneth Casso... | begin core in running state |
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| 2020-07-22 |
Jacob Lifshay | Merge remote-tracking branch 'origin/master' |
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| 2020-07-22 |
Jacob Lifshay | format code |
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