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Handle newer nMigen adding a "bench" hierarchy root in VCD files
[soc.git]
/
src
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soc
/
experiment
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test
/
test_compalu_multi.py
2023-01-01
Cesar Strauss
Handle newer nMigen adding a "bench" hierarchy root...
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2022-10-16
Cesar Strauss
Move test to expose bug in MultiCompUnit
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2021-08-24
Luke Kenneth Casso...
big rename, global/search/replace of ready_o with o_rea...
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2021-07-11
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
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2021-07-10
Cesar Strauss
Detect unexpected operand fetches and produced results
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2021-04-23
Luke Kenneth Casso...
move over to from openpower imports
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2021-01-01
Cesar Strauss
Add zero CR test case and fix comments
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2021-01-01
Cesar Strauss
Add test cases with rc=1
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2021-01-01
Cesar Strauss
Make all ports the same size, on the test ALU
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2021-01-01
Cesar Strauss
Add CR output port to test cases
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2021-01-01
Cesar Strauss
Move NOP test case earlier
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2020-12-31
Cesar Strauss
Implement and test NOP in the test ALU
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2020-12-31
Cesar Strauss
Don't use OP_NOP for zero-delay subtraction
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2020-12-31
Cesar Strauss
Test first input port being masked out
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2020-12-31
Cesar Strauss
Test masked-out second input port
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2020-12-31
Cesar Strauss
Show rdmaskn and wrmask in GTKWave
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2020-12-31
Cesar Strauss
Use the increment operator
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2020-12-31
Cesar Strauss
Add support for masked write operations
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2020-12-31
Cesar Strauss
Clarify reason for holding rdmaskn valid during the...
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2020-12-31
Cesar Strauss
Remove previous version of the CompUnit parallel unit...
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2020-12-31
Cesar Strauss
Only hold the decoder signals for one cycle, along...
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2020-12-30
Cesar Strauss
Test the rdmaskn control signal
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2020-12-07
Cesar Strauss
Display the instruction type as a vector on cxxsim
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2020-12-06
Cesar Strauss
Update GTKWave documents to work with latest cxxsim
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2020-11-24
Cesar Strauss
Fix some typos and whitespace
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2020-11-24
Cesar Strauss
Port the DummyALU test case to the new parallel issuer
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2020-11-23
Cesar Strauss
Results are now a list, so "expected" should follow...
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2020-11-23
Cesar Strauss
Parameterize the issuer on the number of operands and...
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2020-11-22
Cesar Strauss
Refactor the ALU operation issuer into a class
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2020-11-22
Cesar Strauss
Port the ALU test case to the new parallel test style
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2020-11-22
Cesar Strauss
Add a GTKWave document to the ALU test case
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2020-11-19
Cesar Strauss
Separate input and output ports by color
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2020-11-19
Cesar Strauss
Explain the test cases
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2020-11-18
Cesar Strauss
Separate individual traces for each rel_o/go_i port
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2020-11-16
Cesar Strauss
Add a transaction counter to producers and consumers
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2020-11-15
Cesar Strauss
Implement ResultConsumer and port the Shifter unit...
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2020-11-14
Cesar Strauss
Move the DUT driver to within the test case process
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2020-11-14
Cesar Strauss
Fix and enable the regspec test for the Shifter
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2020-10-28
Cesar Strauss
Implement an operand producer that talks the rel_o...
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2020-10-01
Cesar Strauss
Add GTKWave document to test_compunit_fsm
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2020-09-27
Cesar Strauss
Convert yet another few tests to be able to use latest...
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2020-09-07
Luke Kenneth Casso...
bit of a big reorg of data structures
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2020-08-24
Cole Poirier
Merge branch 'master' of git.libre-soc.org:soc
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2020-08-22
Luke Kenneth Casso...
rename invert_a to invert_in because logical inverts RB
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2020-07-29
Luke Kenneth Casso...
bit of a big change: add prefixes "cu_" to all CompUnit...
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2020-07-22
Jacob Lifshay
Merge remote-tracking branch 'origin/master'
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2020-07-22
Jacob Lifshay
format code
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2020-07-21
Luke Kenneth Casso...
testing if MultiCompUnit can handle no input regs ...
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2020-07-21
Luke Kenneth Casso...
disable cxxsim for now
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2020-07-19
Luke Kenneth Casso...
convert compalu multi test to Simulator() (was run_simu...
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2020-07-19
Luke Kenneth Casso...
convert compalu multi test to Simulator() (was run_simu...
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2020-07-19
Luke Kenneth Casso...
add some CompUnit demo tests of the alu_fsm example
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2020-07-12
Luke Kenneth Casso...
rename InternalOp to MicrOp
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2020-06-28
Cesar Strauss
Start with a simpler test case
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2020-06-09
Cesar Strauss
Avoid a combinatorial loop on valid_o
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2020-06-03
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-06-03
Cesar Strauss
Check completion of the sub-processes
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2020-06-03
Cesar Strauss
Simplify immediate check
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2020-06-03
Cesar Strauss
Preliminary check of the alu protocol
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2020-06-03
Cesar Strauss
Pass along the operand, in the cycle in which go is...
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2020-06-02
Cesar Strauss
Allow at least one operand to be fetched
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2020-06-02
Cesar Strauss
Hold rdmaskn active during the busy_o cycle
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2020-06-01
Cesar Strauss
Add rdmaskn parameter and assert it along issue_i
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2020-05-31
Luke Kenneth Casso...
add comments for MultiCompUnit parallel test
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2020-05-31
Luke Kenneth Casso...
remove unneeded imports
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2020-05-31
Luke Kenneth Casso...
split out compalu unit tests to separate module (gettin...
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