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Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
[soc.git]
/
src
/
soc
/
regfile
/
regfiles.py
2020-09-06
Luke Kenneth Casso...
minor code-munge on SPR-to-FAST mapping
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2020-09-06
Luke Kenneth Casso...
move DEC and TB from StateRegs to FastRegs for several...
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2020-09-06
Luke Kenneth Casso...
add DEC and TB to State regfile
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2020-08-31
Luke Kenneth Casso...
add XER to fastregs and "construct" it in mfspr/mtspr
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2020-08-25
Cole Poirier
Merge branch 'master' of git.libre-soc.org:soc
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2020-08-25
Luke Kenneth Casso...
add CR read to DMI interface
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2020-08-14
Luke Kenneth Casso...
put multi-ports back (for read) on int and fast regfiles
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2020-08-13
Luke Kenneth Casso...
sigh. convert Fast regfile to binary
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2020-08-13
Luke Kenneth Casso...
sigh. convert INT regfile to binary addressing
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2020-08-13
Luke Kenneth Casso...
create a RegFileMem class that uses Memory
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2020-08-11
Luke Kenneth Casso...
sigh, remove yet another int regfile read port
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2020-08-11
Luke Kenneth Casso...
reduce regfile port usage for INT and FAST
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2020-08-11
Luke Kenneth Casso...
reduce regfile ports by creating separate STATE regfile
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2020-08-11
Luke Kenneth Casso...
reducing regfile port usage by sharing read ports
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2020-08-03
Luke Kenneth Casso...
add extra port for debug read of int regs via DMI
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2020-07-22
Luke Kenneth Casso...
reduce number of FastRegs read ports
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2020-07-14
Luke Kenneth Casso...
add MSR reading to issue FSM
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2020-07-08
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-05
Luke Kenneth Casso...
add slow spr regfile regspec support
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2020-07-04
Luke Kenneth Casso...
more rename spr1/spr2 to fast1/fast2
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2020-06-18
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-06-18
Luke Kenneth Casso...
slightly hacky way to keep an eye on the PC
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2020-06-16
Luke Kenneth Casso...
add test instruction memory SRAM
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2020-06-05
Luke Kenneth Casso...
name regfile ports by name not numerical position
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2020-06-05
Luke Kenneth Casso...
whoops connecting up CR in wrong order. fixing with...
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2020-06-05
Luke Kenneth Casso...
fix syntax errors and use correct FastRegs (SRR0/1...
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2020-06-04
Luke Kenneth Casso...
initialise XER from simulation
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2020-06-04
Luke Kenneth Casso...
missing a fastregs write-port
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2020-06-03
Luke Kenneth Casso...
connect read-enable and src_i to regfile ports
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2020-06-03
Luke Kenneth Casso...
start putting a non-production core together,
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2020-06-03
Luke Kenneth Casso...
decide to elaborate Refiles *into* another class, rathe...
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2020-06-03
Luke Kenneth Casso...
turn RegFiles into module, add all regfiles to it
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2020-06-03
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-06-03
Luke Kenneth Casso...
add class containing all regfiles
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2020-06-02
Luke Kenneth Casso...
whoops cut/paste error, creating write_ports not read_ports
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2020-05-27
Luke Kenneth Casso...
add extra INT regs port for now, add Fast Regfile
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2020-05-27
Luke Kenneth Casso...
added XER and CR regfiles, using new VirtualRegPort
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2020-05-25
Luke Kenneth Casso...
add INT, SPR and CR regfiles
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2020-05-24
Luke Kenneth Casso...
add stub regfiles.py
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