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Simplify obtaining the PC from the register file
[soc.git]
/
src
/
soc
/
simple
/
test
/
test_core.py
2021-02-15
Cesar Strauss
Simplify obtaining the PC from the register file
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2021-02-15
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
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2021-02-13
Cesar Strauss
Check the PC value at the end of each instruction
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2021-01-18
Tobias Platen
uncomment #FIXME in unit_test
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2021-01-08
Tobias Platen
fix broken testcase for simple core
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2020-08-15
Luke Kenneth Casso...
rather big change to interaction between regfile and...
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2020-08-14
Luke Kenneth Casso...
move instruction decoder out of core
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2020-08-13
Luke Kenneth Casso...
sigh. convert INT regfile to binary addressing
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2020-08-03
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-08-03
Luke Kenneth Casso...
change over to DMI debug start/stop interface
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2020-07-22
Jacob Lifshay
Merge remote-tracking branch 'origin/master'
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2020-07-22
Jacob Lifshay
format code
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2020-07-11
Luke Kenneth Casso...
fix spr setting, set endianness
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2020-07-08
Luke Kenneth Casso...
resolving old and new behaviour for lookup of SPRs
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2020-07-08
Luke Kenneth Casso...
resolving old and new behaviour for lookup of SPRs
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2020-07-08
Luke Kenneth Casso...
adding in ALU test back in, debugging SPR setup
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2020-07-08
Luke Kenneth Casso...
sorting out setting of XER
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2020-07-08
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-07
Luke Kenneth Casso...
ordering of tests for OP_ATTN needed shuffling. seems...
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2020-07-07
Luke Kenneth Casso...
debugging termination (OP_ATTN)
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2020-07-07
Luke Kenneth Casso...
debugging termination / OP_ATTN
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2020-07-05
Luke Kenneth Casso...
big reorg on PowerDecoder2, actually Decode2Execute1Type
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2020-07-04
Luke Kenneth Casso...
add pspec to test_core.py
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2020-07-04
Luke Kenneth Casso...
add pspec to test_core.py
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2020-06-17
Luke Kenneth Casso...
enable all tests again in test_core.py and test_issuer.py
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2020-06-17
Luke Kenneth Casso...
debugging test_issuer, getting FSM working
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2020-06-16
Luke Kenneth Casso...
reduce instruction depth to 6 bits in TestIssuer
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2020-06-16
Luke Kenneth Casso...
move debug statements to check function
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2020-06-16
Luke Kenneth Casso...
move check regs in simple core to separate function
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2020-06-16
Luke Kenneth Casso...
move test core reg set up into separate function
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2020-06-16
Luke Kenneth Casso...
add beginnings of TestIssuer class, to issue instructio...
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2020-06-16
Luke Kenneth Casso...
refer to signals directly in Test Core
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2020-06-15
Luke Kenneth Casso...
have to set up addr/st rel-go link before setting up...
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2020-06-15
Luke Kenneth Casso...
add in memory setup/check but disable LDST Unit Tests...
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2020-06-08
Luke Kenneth Casso...
re-add unit tests back in
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2020-06-08
Luke Kenneth Casso...
more verbose debug information tracking down SO/OV...
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2020-06-08
Luke Kenneth Casso...
code-morph test_core for XER bit clarity
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2020-06-08
Luke Kenneth Casso...
added check which shows that OV32 in "adde." is not...
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2020-06-07
Luke Kenneth Casso...
assert XER SO/OV/CA registers, check these are ok ...
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2020-06-07
Luke Kenneth Casso...
add debug print statements, re-enable all tests in...
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2020-06-07
Luke Kenneth Casso...
add msr to ISA in test_core.py
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2020-06-06
Luke Kenneth Casso...
missing test.mem arg for ISA in test_core
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2020-06-05
Luke Kenneth Casso...
comment out CR assertion for now
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2020-06-05
Luke Kenneth Casso...
experimenting with CR, not quite right
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2020-06-04
Luke Kenneth Casso...
testing CRs after writing: not in the right bit-order
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2020-06-04
Luke Kenneth Casso...
remove unneeded code
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2020-06-04
Luke Kenneth Casso...
add branch test case to core
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2020-06-04
Luke Kenneth Casso...
no global variables in test suites
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2020-06-04
Luke Kenneth Casso...
sigh. because POWER. CR index inversion
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2020-06-04
Luke Kenneth Casso...
sigh. weirdness involving bit-inversion, inconsistency...
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2020-06-04
Luke Kenneth Casso...
no global variables in test suites
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2020-06-04
Luke Kenneth Casso...
add ShiftRot test case (works only because CRs are...
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2020-06-04
Luke Kenneth Casso...
add both logical and ALU test core
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2020-06-04
Luke Kenneth Casso...
comment clarify on core
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2020-06-04
Luke Kenneth Casso...
initialise XER from simulation
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2020-06-04
Luke Kenneth Casso...
messing with valid/busy signals in core test
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2020-06-04
Luke Kenneth Casso...
test actual reg values being produced in core test
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2020-06-04
Luke Kenneth Casso...
move reg setup to earlier in test
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2020-06-04
Luke Kenneth Casso...
test against Logical (hard-coded change)
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2020-06-04
Luke Kenneth Casso...
add first cut at test core
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