Remove extra wait on core_stop_o at end of Execute.
[soc.git] / src / soc / simple /
2021-12-23 Cesar StraussRemove extra wait on core_stop_o at end of Execute.
2021-12-23 Cesar StraussRe-enable core stopped signal when stopped.
2021-12-22 Luke Kenneth Casso... fix issues with running core in DMI "stopped" status...
2021-12-22 Luke Kenneth Casso... whoops, use MSR.IR for I-Cache fetch!
2021-12-21 Luke Kenneth Casso... continue to assert PC in FetchFSM if needed
2021-12-21 Luke Kenneth Casso... enable I-Cache wishbone memory type in issuer_verilog...
2021-12-21 Luke Kenneth Casso... whoops issuer_verilog.py enabling mmu has to pass micro...
2021-12-21 Luke Kenneth Casso... for each unit test case in test_issuer_mmu_data_path...
2021-12-21 Luke Kenneth Casso... test_issuer_mmu_data_path.py needs to use wb_get because of
2021-12-20 Luke Kenneth Casso... set up DAR correctly in unit tests, added set_ldst_spr...
2021-12-19 Luke Kenneth Casso... add hard stop address in ifetch unit test, bit of a...
2021-12-19 Luke Kenneth Casso... set terminate if core terminate requested
2021-12-19 Luke Kenneth Casso... add DMI STOPADDR register and use it in HDLRunner to...
2021-12-19 Luke Kenneth Casso... break out when core is stopped in HDLRunner
2021-12-18 Luke Kenneth Casso... sort out reset signalling after tracking down Simulatio...
2021-12-18 Luke Kenneth Casso... add icache/dcache/mmu unit test for TestIssuer
2021-12-18 Luke Kenneth Casso... get instructions to re-run in issuer after I-Cache...
2021-12-16 Luke Kenneth Casso... set_mmu_spr was using the slow-SPR index for the regfile
2021-12-16 Luke Kenneth Casso... whoops remove duplicate code (cut/paste error) no harm...
2021-12-15 Luke Kenneth Casso... remove more unneeded code
2021-12-15 Luke Kenneth Casso... read MSR.PR and MSR.DR and update ICache priv/virt...
2021-12-15 Luke Kenneth Casso... remove more of SVP64 from TestIssuerInternalInOrder
2021-12-15 Luke Kenneth Casso... remove update of pc, msr and svstate from TestIssuerInOrder
2021-12-15 Luke Kenneth Casso... move update of pc, msr and svstate into TestIssuerBase
2021-12-15 Luke Kenneth Casso... comment-out TestIssuerInternalInorder for now
2021-12-15 Luke Kenneth Casso... move alternative TestIssuerInternalInOrder to new file
2021-12-15 Luke Kenneth Casso... split out common elaboratable code from TestIssuer,
2021-12-15 Luke Kenneth Casso... big split-out of common functions in TestIssuer to...
2021-12-15 Luke Kenneth Casso... simplifying / tidyup of TestIssuer to get CoreState
2021-12-15 Luke Kenneth Casso... sort out MSR, read/write in same way as PC/SVSTATE...
2021-12-15 Luke Kenneth Casso... whoops accidentally commented out setup of instructions
2021-12-15 Luke Kenneth Casso... get fetch_failed working with no MMU
2021-12-14 Luke Kenneth Casso... trying to get TestIssuer FSM to respond correctly to...
2021-12-14 Luke Kenneth Casso... update wb_get memory with instructions if required
2021-12-13 Luke Kenneth Casso... request a flush of icache to clear the instruction...
2021-12-12 Luke Kenneth Casso... set and reset instruction fault so it does not occur...
2021-12-12 Luke Kenneth Casso... when an exception happens, if it is a fetch_failed...
2021-12-12 Luke Kenneth Casso... drat, a test inverting the instruction made it into...
2021-12-12 Luke Kenneth Casso... starting to hack in fetch failed (including OP_FETCH_FA...
2021-12-12 Luke Kenneth Casso... print debugs established that when a wb_get memory...
2021-12-12 Luke Kenneth Casso... set fetch_failed into PowerDecoder2 combinatorially
2021-12-12 Luke Kenneth Casso... in a terrible botched way, get at I-Cache and set it up
2021-12-11 Luke Kenneth Casso... connect up I-Cache to FetchUnitInterface
2021-12-09 Luke Kenneth Casso... wire fetch_failed from I-Cache to PowerDecoder2
2021-12-09 Luke Kenneth Casso... make icache accessible to core, working back to TestIssuer
2021-12-09 Jacob Lifshaymake argv handling more flexible
2021-12-09 Jacob Lifshayformat code
2021-12-05 Luke Kenneth Casso... correct import of wg_get function
2021-12-04 Luke Kenneth Casso... whoops
2021-12-04 Luke Kenneth Casso... MMU lookup DSISR load bit inverted in LoadStore1
2021-12-03 Luke Kenneth Casso... add misaligned ld/st to trigger an exception
2021-12-02 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-12-02 Luke Kenneth Casso... add a bitvector remap function, the plan is to use...
2021-12-02 Luke Kenneth Casso... use new namedtuple in core when calling regspec_decode()
2021-12-02 Luke Kenneth Casso... add module parameter to regspec_decode and therefore...
2021-12-01 Luke Kenneth Casso... stack of changes to MultiCompUnit to speed it up
2021-12-01 Luke Kenneth Casso... FunctionUnitBaseMulti which derives from ReservationSta...
2021-12-01 Luke Kenneth Casso... better name for read latch in core.py
2021-12-01 Luke Kenneth Casso... remove redundant / mis-named variable in core
2021-12-01 Luke Kenneth Casso... code-comments
2021-12-01 Luke Kenneth Casso... remove unneeded data structure in core
2021-12-01 Luke Kenneth Casso... whoops treereduce on write-vector set/clr error
2021-12-01 Luke Kenneth Casso... more code-cleanup
2021-12-01 Luke Kenneth Casso... use new regspec_decode and fu.get_iospec functions
2021-12-01 Luke Kenneth Casso... core tidyup
2021-11-30 Luke Kenneth Casso... start allocating more FUs (more ReservationStations)
2021-11-30 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-30 Luke Kenneth Casso... add LogicalTestCases back in to test_core.py (pass)
2021-11-30 Luke Kenneth Casso... let PowerDecode2 decide which operand class to use...
2021-11-30 Luke Kenneth Casso... use latched readflag (recspec_decode_read "ok") instead...
2021-11-30 Luke Kenneth Casso... tidyup on read-flag latches
2021-11-30 Luke Kenneth Casso... fix read-decode information by latching not just the...
2021-11-30 Luke Kenneth Casso... fix write-after-write hazard checking
2021-11-30 Luke Kenneth Casso... allow busy to settle before checking state in test_core.py
2021-11-30 Luke Kenneth Casso... only check regs right at the end in test_core.py overla...
2021-11-30 Luke Kenneth Casso... move sim call before core run in test_core.py
2021-11-30 Luke Kenneth Casso... getting formerly unused test_core.py operational
2021-11-29 Luke Kenneth Casso... whoops missed make_hazard_vec test
2021-11-29 Luke Kenneth Casso... whoops do the set/get of the write-vector at a single...
2021-11-29 Luke Kenneth Casso... add MMU and SPR to list of FUs that must report "busy...
2021-11-29 Luke Kenneth Casso... disallow overlap in core on LDST, Branch, and Trap.
2021-11-29 Luke Kenneth Casso... use dict style not setattr on submodules
2021-11-27 Luke Kenneth Casso... code-comments
2021-11-27 Luke Kenneth Casso... fix instructions of the type "read-reg-is-same-as-write"
2021-11-24 Luke Kenneth Casso... convert hazard bitvectors to Reset-Priority SRLatch...
2021-11-24 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-24 Luke Kenneth Casso... fix write-after-write hazard detection
2021-11-24 Luke Kenneth Casso... when allow_overlap enabled do a manual wait until all...
2021-11-24 Luke Kenneth Casso... code-comments
2021-11-24 Luke Kenneth Casso... add write-after-write hazard detection
2021-11-24 Luke Kenneth Casso... whoops merged the two write-ports for RT and RA-with...
2021-11-24 Luke Kenneth Casso... disable hazard vectors when overlap is not requested...
2021-11-23 Luke Kenneth Casso... more comments
2021-11-23 Luke Kenneth Casso... add FU write-after-write hazard detection Signal (dummy...
2021-11-23 Luke Kenneth Casso... add code-comments, link to in-order core
2021-11-23 Luke Kenneth Casso... more use of namedtuples in core.py for clarity
2021-11-23 Luke Kenneth Casso... start some use of namedtuples in core.py
2021-11-23 Luke Kenneth Casso... use some namedtuples to make things clearer in core.py
2021-11-23 Luke Kenneth Casso... use fascinating trick of defaultdict-of-defaultdicts
2021-11-22 Luke Kenneth Casso... make FetchFSM take PC as an input in its ispec
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