| 2022-02-09 |
Luke Kenneth Casson... | add opencores uart16550 instance wrapper
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| 2022-01-31 |
Luke Kenneth Casson... | fix bug in itlb_valid SRLatch set/reset, a bit weird...
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| 2022-01-31 |
Luke Kenneth Casson... | whoops tlb_valids in ICache is a combinatorial-get/set
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| 2022-01-31 |
Luke Kenneth Casson... | convert TLBValidArray in ICache to SRLatch
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| 2022-01-31 |
Luke Kenneth Casson... | add microwatt external core build target to Makefile
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| 2022-01-31 |
Luke Kenneth Casson... | use an SRLatch for cache_valids, at least it reduces...
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| 2022-01-31 |
Luke Kenneth Casson... | use Memory for cache tags in dcache
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commit | commitdiff | tree |
| 2022-01-31 |
Luke Kenneth Casson... | use Memory for cache_tags in icache
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| 2022-01-31 |
Luke Kenneth Casson... | doh
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| 2022-01-31 |
Luke Kenneth Casson... | remove dummy trap pipeline
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| 2022-01-31 |
Luke Kenneth Casson... | remove combinatorial loop from MultiCompUnit
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| 2022-01-30 |
Luke Kenneth Casson... | break out cache_tags and cache_valids (again) this...
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| 2022-01-30 |
Luke Kenneth Casson... | remove CacheTagArray in icache.py
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| 2022-01-30 |
Luke Kenneth Casson... | create Memory for Cache Tags in I-Cache
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| 2022-01-30 |
Luke Kenneth Casson... | remove unneeded parameter
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| 2022-01-30 |
Luke Kenneth Casson... | add Array of CacheValids back in, so as to reduce LUT4...
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| 2022-01-30 |
Luke Kenneth Casson... | tagset is a local Signal in ICache
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| 2022-01-30 |
Luke Kenneth Casson... | identify combinatorial loop signals in MultiCompUnit...
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| 2022-01-30 |
Luke Kenneth Casson... | use nmigen Memory in I-Cache for TLB Lookups
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| 2022-01-30 |
Luke Kenneth Casson... | put itlb_valid back, ready for conversion to Memory...
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| 2022-01-30 |
Luke Kenneth Casson... | convert CacheRAM to Memory, acts much faster now
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| 2022-01-29 |
Luke Kenneth Casson... | explanatory comment when page hit is the same for stores
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commit | commitdiff | tree |
| 2022-01-29 |
Luke Kenneth Casson... | use right offset in dcache wb address
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| 2022-01-29 |
Luke Kenneth Casson... | re-examining dcache.vhdl, still did not get the store...
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| 2022-01-29 |
Luke Kenneth Casson... | bug in dcache.py where when two stores occur in the...
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| 2022-01-28 |
Luke Kenneth Casson... | in LoadStore1 capture the address for misaligned dual...
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commit | commitdiff | tree |
| 2022-01-28 |
Luke Kenneth Casson... | sort out misaligned store in LoadStore1
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| 2022-01-27 |
Luke Kenneth Casson... | for second aligned request truncate address to nearest...
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| 2022-01-25 |
Luke Kenneth Casson... | add license and copyright header to dcache.py,
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| 2022-01-25 |
Luke Kenneth Casson... | LDSTException now passing bits of SRR1 around to the...
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| 2022-01-24 |
Luke Kenneth Casson... | comments
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| 2022-01-24 |
Luke Kenneth Casson... | hmm there seems to have been an error in DTLB Read,
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| 2022-01-24 |
Luke Kenneth Casson... | bool test on traptype to
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| 2022-01-23 |
Luke Kenneth Casson... | looked in soc.vhdl in microwatt and the parameters...
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| 2022-01-23 |
Luke Kenneth Casson... | add debug output of whether stall occurs on dcache
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| 2022-01-22 |
Luke Kenneth Casson... | missed setting of r0_full to zero in dcache. not encountered as
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| 2022-01-21 |
Luke Kenneth Casson... | skip ilang data in branch test_pipe_caller.py
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| 2022-01-21 |
Luke Kenneth Casson... | attempting to get compunit and test_pipe_caller unit...
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| 2022-01-21 |
Luke Kenneth Casson... | sigh, monitor DEC/TB StateRegs "properly" so that the...
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commit | commitdiff | tree |
| 2022-01-21 |
Luke Kenneth Casson... | whoops fix bug in setting of DEC/TB (State) in test_core.py
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commit | commitdiff | tree |
| 2022-01-20 |
Luke Kenneth Casson... | whoops MFSPR DEC/TB was reading from FastRegs not StateRegs
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| 2022-01-19 |
Luke Kenneth Casson... | whoops forgot to enable fast-reg read in DMI
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commit | commitdiff | tree |
| 2022-01-19 |
Luke Kenneth Casson... | ISI (0x400) trap is the only one that puts memory-based...
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commit | commitdiff | tree |
| 2022-01-19 |
Luke Kenneth Casson... | comments
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commit | commitdiff | tree |
| 2022-01-19 |
Luke Kenneth Casson... | move DEC and TB into StateRegs, to make room in FastRegs
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| 2022-01-18 |
Luke Kenneth Casson... | add support for DMI debug read of FAST Regfile SPRs
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commit | commitdiff | tree |
| 2022-01-18 |
Luke Kenneth Casson... | comments on SRR1 in trap
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commit | commitdiff | tree |
| 2022-01-18 |
Luke Kenneth Casson... | preserve bits of SRR1 on a TRAP (including all interrupts...
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commit | commitdiff | tree |
| 2022-01-17 |
Luke Kenneth Casson... | fix hrfid and mtmsrd so that it is identical to microwatt
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| 2022-01-17 |
Luke Kenneth Casson... | connect up DEC/TB FSM pauser from core to Issuer
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commit | commitdiff | tree |
| 2022-01-17 |
Luke Kenneth Casson... | comments
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commit | commitdiff | tree |
| 2022-01-17 |
Luke Kenneth Casson... | whitespace
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commit | commitdiff | tree |
| 2022-01-17 |
Luke Kenneth Casson... | add pause_dec_tb signal (not very sophisticated) to...
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| 2022-01-17 |
Luke Kenneth Casson... | add signal for pausing the DEC/TB FSM to IssuerBase
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| 2022-01-16 |
Luke Kenneth Casson... | raise interrupt on misaligned atomic LDST
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| 2022-01-16 |
Luke Kenneth Casson... | pass over store_done correctly from dcache over PortInterface
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| 2022-01-16 |
Luke Kenneth Casson... | add CR0 to LDSTCompUnit, for reporting if LR/SC store...
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| 2022-01-16 |
Luke Kenneth Casson... | remove PortInterface mmu_done signal,
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commit | commitdiff | tree |
| 2022-01-15 |
Luke Kenneth Casson... | forgot name on dcache Reservation
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commit | commitdiff | tree |
| 2022-01-15 |
Luke Kenneth Casson... | pass over atomic signals to dcache from loadstore.
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commit | commitdiff | tree |
| 2022-01-15 |
Luke Kenneth Casson... | try using req.op in RELOAD_WAIT_ACK to detect whether...
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commit | commitdiff | tree |
| 2022-01-15 |
Luke Kenneth Casson... | pass atomic reserve through from PortInterface to DCache
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commit | commitdiff | tree |
| 2022-01-15 |
Luke Kenneth Casson... | add atomic LR/SC signal to LDSTCompUnit
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commit | commitdiff | tree |
| 2022-01-15 |
Luke Kenneth Casson... | add reserve (atomic) signal to LDST data structures...
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commit | commitdiff | tree |
| 2022-01-15 |
Luke Kenneth Casson... | tidyup PortInterface
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commit | commitdiff | tree |
| 2022-01-15 |
Luke Kenneth Casson... | workaround for bug in dcache where the r1.req waiting...
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commit | commitdiff | tree |
| 2022-01-15 |
Luke Kenneth Casson... | enable both linux-5.7 tests
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commit | commitdiff | tree |
| 2022-01-14 |
Luke Kenneth Casson... | split out CacheTag Record to separate structure
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commit | commitdiff | tree |
| 2022-01-14 |
Luke Kenneth Casson... | update how d_valid is handled
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commit | commitdiff | tree |
| 2022-01-14 |
Luke Kenneth Casson... | missed setting r1.store_way and r1.store_row in STORE_WAIT_A...
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commit | commitdiff | tree |
| 2022-01-14 |
Luke Kenneth Casson... | Revert "dcache 2nd stage (r1) should only indicate...
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commit | commitdiff | tree |
| 2022-01-14 |
Luke Kenneth Casson... | second test for linux-5.7
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commit | commitdiff | tree |
| 2022-01-12 |
Luke Kenneth Casson... | add allow-overlap option to issuer_verilog.py
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| 2022-01-12 |
Luke Kenneth Casson... | dcache 2nd stage (r1) should only indicate not-busy
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commit | commitdiff | tree |
| 2022-01-12 |
Luke Kenneth Casson... | fix issue with priv_mode not being passed correctly...
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commit | commitdiff | tree |
| 2022-01-12 |
Luke Kenneth Casson... | fix issue with d_valid in dcache, was not being set...
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commit | commitdiff | tree |
| 2022-01-10 |
Luke Kenneth Casson... | LoadStore1 priv_mode was not being correctly picked...
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commit | commitdiff | tree |
| 2022-01-09 |
Luke Kenneth Casson... | grab the LDST request address for microwatt verilator...
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commit | commitdiff | tree |
| 2022-01-09 |
Luke Kenneth Casson... | add linux-5.7 unit test which showed a silly error:
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commit | commitdiff | tree |
| 2022-01-08 |
Luke Kenneth Casson... | fix MMU lookup after 2nd request (misaligned) by also...
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commit | commitdiff | tree |
| 2022-01-08 |
Luke Kenneth Casson... | add microwatt mmu.bin test5 to show page-fault on misaligned LD
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commit | commitdiff | tree |
| 2022-01-08 |
Luke Kenneth Casson... | do not clear out ldst request after TLB entry is added
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commit | commitdiff | tree |
| 2022-01-08 |
Luke Kenneth Casson... | enable microwatt mmu test2
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commit | commitdiff | tree |
| 2022-01-08 |
Luke Kenneth Casson... | whitespace and use exc is None not exc == None
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commit | commitdiff | tree |
| 2022-01-08 |
Luke Kenneth Casson... | add a second LD request to dcache which is merged with...
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commit | commitdiff | tree |
| 2022-01-08 |
Luke Kenneth Casson... | start adding in mis-aligned LD/ST support into LoadStore1
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commit | commitdiff | tree |
| 2022-01-07 |
Luke Kenneth Casson... | whitespace
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commit | commitdiff | tree |
| 2022-01-07 |
Luke Kenneth Casson... | add missing MSRSpec import
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commit | commitdiff | tree |
| 2022-01-07 |
Luke Kenneth Casson... | add msr_o to issuer in microwatt_compat mode
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| 2022-01-06 |
Luke Kenneth Casson... | double the number of lines in the L1 D/I-Cache to match...
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| 2022-01-06 |
Luke Kenneth Casson... | add SECOND_REQ state to loadstore.py, not yet implemented
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| 2022-01-05 |
Luke Kenneth Casson... | add easy-to-access debug reporting of instruction and PC
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| 2022-01-05 |
Luke Kenneth Casson... | use microwatt-specific PLRU due to bug in nmutil version
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| 2022-01-04 |
Luke Kenneth Casson... | fix DriverConflict over MSR write in Issuer/Core by...
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| 2022-01-04 |
Luke Kenneth Casson... | remove FetchFSM from TestIssuer (it served its purpose...
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| 2022-01-03 |
Luke Kenneth Casson... | doh, bus-hack was the wrong way round. *output* the...
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commit | commitdiff | tree |
| 2022-01-03 |
Luke Kenneth Casson... | sigh, microwatts wishbone bus usage is non-wishbone...
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| 2022-01-03 |
Luke Kenneth Casson... | sigh have to allow external clocks and reset mess even...
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commit | commitdiff | tree |
| 2022-01-03 |
Luke Kenneth Casson... | give module appropriate top-level name in microwatt...
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commit | commitdiff | tree |
| 2022-01-03 |
Luke Kenneth Casson... | add missing ext_irq signal to testissuer in microwatt...
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