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add logical test issuer case
[soc.git]
/
src
/
soc
/
simple
/
test
/
test_issuer.py
2020-08-09
Luke Kenneth Casso...
add logical test issuer case
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2020-08-05
Cole Poirier
Merge branch 'master' of git.libre-soc.org:soc
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2020-08-05
Luke Kenneth Casso...
add div test cases into test_issuer.py
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2020-08-03
Luke Kenneth Casso...
add quick demo/test of reading DMI reg 9
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2020-08-03
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-08-03
Luke Kenneth Casso...
change over to DMI debug start/stop interface
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2020-07-29
Jacob Lifshay
format some tests
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2020-07-26
Luke Kenneth Casso...
add nop test cases
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2020-07-26
Luke Kenneth Casso...
activate some of new accumulator-based tests in test_issuer
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2020-07-23
Luke Kenneth Casso...
support 32-bit mem width setting
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2020-07-22
Jacob Lifshay
Merge remote-tracking branch 'origin/master'
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2020-07-22
Jacob Lifshay
format code
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2020-07-19
Luke Kenneth Casso...
update to expose signals at top-level of issuer
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2020-07-19
Luke Kenneth Casso...
add DivTestCase to test_issuer.py (commented out for...
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2020-07-12
Luke Kenneth Casso...
add OP_ATTN test back in
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2020-07-12
Luke Kenneth Casso...
msb of instruction causing sign-overflow
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2020-07-11
Luke Kenneth Casso...
more setting bigendian
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2020-07-08
Luke Kenneth Casso...
resolving bigendian/littleendian modes in qemu sim
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2020-07-08
Luke Kenneth Casso...
adding in ALU test back in, debugging SPR setup
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2020-07-08
Luke Kenneth Casso...
got test_issuer operational on one unit test
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2020-07-08
Luke Kenneth Casso...
stashing current state of investigation whilst looking...
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2020-07-08
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-07
Luke Kenneth Casso...
sort-of got binary execution test working
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2020-07-07
Luke Kenneth Casso...
code-shuffle on testing to prepare loading large files...
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2020-07-07
Luke Kenneth Casso...
debugging termination (OP_ATTN)
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2020-07-07
Luke Kenneth Casso...
update opcode map for OP_ATTN
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2020-07-07
Luke Kenneth Casso...
debugging termination / OP_ATTN
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2020-07-07
Luke Kenneth Casso...
add core start/stop capability, and OP_ATTN support
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2020-07-07
Luke Kenneth Casso...
add in SPR test cases into test_issuer.py
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2020-07-05
Luke Kenneth Casso...
add SPR test case, commented out for now
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2020-07-02
Luke Kenneth Casso...
use single-arg pspec for TestIssuer and Core
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2020-06-29
Luke Kenneth Casso...
fetch instructions from bare wishbone fetch unit
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2020-06-28
Luke Kenneth Casso...
read from instruction memory using FetchUnitInterface
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2020-06-28
Luke Kenneth Casso...
expand instruction bus width to 64 bit, start on a...
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2020-06-27
Luke Kenneth Casso...
make PortInterface modules consistent with same API
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2020-06-18
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-06-18
Luke Kenneth Casso...
enable general test cases in test_issuer
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2020-06-18
Luke Kenneth Casso...
use different way to pass instructions to test_issuer...
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2020-06-18
Luke Kenneth Casso...
debugging test_issuer.py general test cases
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2020-06-17
Luke Kenneth Casso...
split out TestIssuer into separate module
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2020-06-17
Luke Kenneth Casso...
remove unneeded yield
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2020-06-17
Luke Kenneth Casso...
enable all tests again in test_core.py and test_issuer.py
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2020-06-17
Luke Kenneth Casso...
got test_issuer FSM operating. bit of a hack
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2020-06-17
Luke Kenneth Casso...
debugging test_issuer, getting FSM working
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2020-06-17
Luke Kenneth Casso...
output to issuer_simulator.vcd
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2020-06-16
Luke Kenneth Casso...
add first version unit test for TestIssuer
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