2022-01-05 |
Luke Kenneth Casso... | add easy-to-access debug reporting of instruction and PC |
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2022-01-04 |
Luke Kenneth Casso... | fix DriverConflict over MSR write in Issuer/Core by... |
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2022-01-04 |
Luke Kenneth Casso... | remove FetchFSM from TestIssuer (it served its purpose... |
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2022-01-03 |
Luke Kenneth Casso... | doh, bus-hack was the wrong way round. *output* the... |
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2022-01-03 |
Luke Kenneth Casso... | sigh, microwatts wishbone bus usage is non-wishbone... |
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2022-01-03 |
Luke Kenneth Casso... | sigh have to allow external clocks and reset mess even... |
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2022-01-03 |
Luke Kenneth Casso... | give module appropriate top-level name in microwatt... |
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2022-01-03 |
Luke Kenneth Casso... | add missing ext_irq signal to testissuer in microwatt... |
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2022-01-03 |
Luke Kenneth Casso... | adding an extra option to issuer_verilog.py to be able... |
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2022-01-03 |
Luke Kenneth Casso... | bring external irq out for microwatt-compatible mode... |
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2022-01-03 |
Cesar Strauss | On inorder.py, after Execute, update the PC and go... |
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2021-12-30 |
Luke Kenneth Casso... | rename nia to cia in MMU input record and mmu FSM |
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2021-12-28 |
Cesar Strauss | Add an --inorder option to test_issuer.py |
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2021-12-27 |
Cesar Strauss | Fix indentation |
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2021-12-25 |
Luke Kenneth Casso... | add mmu.bin test2 to much simpler test_loadstore1.py |
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2021-12-25 |
Luke Kenneth Casso... | move microwatt mmu.bin test 3 page table to test pageta... |
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2021-12-25 |
Luke Kenneth Casso... | wait for MMU "done" when setting PRTBL and PIDR |
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2021-12-25 |
Luke Kenneth Casso... | add microwatt mmu.bin regression test test_mmu_3 |
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2021-12-24 |
Luke Kenneth Casso... | enable instruction redirect in mmu ifetch test |
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2021-12-23 |
Luke Kenneth Casso... | allow MSR reset to default to a value set by issuer_ver... |
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2021-12-23 |
Luke Kenneth Casso... | pass in msr_reset to issuer_verilog.py |
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2021-12-23 |
Cesar Strauss | Remove extra wait on core_stop_o at end of Execute. |
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2021-12-23 |
Cesar Strauss | Re-enable core stopped signal when stopped. |
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2021-12-22 |
Luke Kenneth Casso... | fix issues with running core in DMI "stopped" status... |
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2021-12-22 |
Luke Kenneth Casso... | whoops, use MSR.IR for I-Cache fetch! |
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2021-12-21 |
Luke Kenneth Casso... | continue to assert PC in FetchFSM if needed |
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2021-12-21 |
Luke Kenneth Casso... | enable I-Cache wishbone memory type in issuer_verilog... |
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2021-12-21 |
Luke Kenneth Casso... | whoops issuer_verilog.py enabling mmu has to pass micro... |
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2021-12-21 |
Luke Kenneth Casso... | for each unit test case in test_issuer_mmu_data_path... |
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2021-12-21 |
Luke Kenneth Casso... | test_issuer_mmu_data_path.py needs to use wb_get because of |
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2021-12-20 |
Luke Kenneth Casso... | set up DAR correctly in unit tests, added set_ldst_spr... |
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2021-12-19 |
Luke Kenneth Casso... | add hard stop address in ifetch unit test, bit of a... |
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2021-12-19 |
Luke Kenneth Casso... | set terminate if core terminate requested |
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2021-12-19 |
Luke Kenneth Casso... | add DMI STOPADDR register and use it in HDLRunner to... |
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2021-12-19 |
Luke Kenneth Casso... | break out when core is stopped in HDLRunner |
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2021-12-18 |
Luke Kenneth Casso... | sort out reset signalling after tracking down Simulatio... |
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2021-12-18 |
Luke Kenneth Casso... | add icache/dcache/mmu unit test for TestIssuer |
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2021-12-18 |
Luke Kenneth Casso... | get instructions to re-run in issuer after I-Cache... |
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2021-12-16 |
Luke Kenneth Casso... | set_mmu_spr was using the slow-SPR index for the regfile |
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2021-12-16 |
Luke Kenneth Casso... | whoops remove duplicate code (cut/paste error) no harm... |
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2021-12-15 |
Luke Kenneth Casso... | remove more unneeded code |
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2021-12-15 |
Luke Kenneth Casso... | read MSR.PR and MSR.DR and update ICache priv/virt... |
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2021-12-15 |
Luke Kenneth Casso... | remove more of SVP64 from TestIssuerInternalInOrder |
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2021-12-15 |
Luke Kenneth Casso... | remove update of pc, msr and svstate from TestIssuerInOrder |
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2021-12-15 |
Luke Kenneth Casso... | move update of pc, msr and svstate into TestIssuerBase |
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2021-12-15 |
Luke Kenneth Casso... | comment-out TestIssuerInternalInorder for now |
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2021-12-15 |
Luke Kenneth Casso... | move alternative TestIssuerInternalInOrder to new file |
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2021-12-15 |
Luke Kenneth Casso... | split out common elaboratable code from TestIssuer, |
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2021-12-15 |
Luke Kenneth Casso... | big split-out of common functions in TestIssuer to... |
tree | commitdiff |
2021-12-15 |
Luke Kenneth Casso... | simplifying / tidyup of TestIssuer to get CoreState |
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2021-12-15 |
Luke Kenneth Casso... | sort out MSR, read/write in same way as PC/SVSTATE... |
tree | commitdiff |
2021-12-15 |
Luke Kenneth Casso... | whoops accidentally commented out setup of instructions |
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2021-12-15 |
Luke Kenneth Casso... | get fetch_failed working with no MMU |
tree | commitdiff |
2021-12-14 |
Luke Kenneth Casso... | trying to get TestIssuer FSM to respond correctly to... |
tree | commitdiff |
2021-12-14 |
Luke Kenneth Casso... | update wb_get memory with instructions if required |
tree | commitdiff |
2021-12-13 |
Luke Kenneth Casso... | request a flush of icache to clear the instruction... |
tree | commitdiff |
2021-12-12 |
Luke Kenneth Casso... | set and reset instruction fault so it does not occur... |
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2021-12-12 |
Luke Kenneth Casso... | when an exception happens, if it is a fetch_failed... |
tree | commitdiff |
2021-12-12 |
Luke Kenneth Casso... | drat, a test inverting the instruction made it into... |
tree | commitdiff |
2021-12-12 |
Luke Kenneth Casso... | starting to hack in fetch failed (including OP_FETCH_FA... |
tree | commitdiff |
2021-12-12 |
Luke Kenneth Casso... | print debugs established that when a wb_get memory... |
tree | commitdiff |
2021-12-12 |
Luke Kenneth Casso... | set fetch_failed into PowerDecoder2 combinatorially |
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2021-12-12 |
Luke Kenneth Casso... | in a terrible botched way, get at I-Cache and set it up |
tree | commitdiff |
2021-12-11 |
Luke Kenneth Casso... | connect up I-Cache to FetchUnitInterface |
tree | commitdiff |
2021-12-09 |
Luke Kenneth Casso... | wire fetch_failed from I-Cache to PowerDecoder2 |
tree | commitdiff |
2021-12-09 |
Luke Kenneth Casso... | make icache accessible to core, working back to TestIssuer |
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2021-12-09 |
Jacob Lifshay | make argv handling more flexible |
tree | commitdiff |
2021-12-09 |
Jacob Lifshay | format code |
tree | commitdiff |
2021-12-05 |
Luke Kenneth Casso... | correct import of wg_get function |
tree | commitdiff |
2021-12-04 |
Luke Kenneth Casso... | whoops |
tree | commitdiff |
2021-12-04 |
Luke Kenneth Casso... | MMU lookup DSISR load bit inverted in LoadStore1 |
tree | commitdiff |
2021-12-03 |
Luke Kenneth Casso... | add misaligned ld/st to trigger an exception |
tree | commitdiff |
2021-12-02 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2021-12-02 |
Luke Kenneth Casso... | add a bitvector remap function, the plan is to use... |
tree | commitdiff |
2021-12-02 |
Luke Kenneth Casso... | use new namedtuple in core when calling regspec_decode() |
tree | commitdiff |
2021-12-02 |
Luke Kenneth Casso... | add module parameter to regspec_decode and therefore... |
tree | commitdiff |
2021-12-01 |
Luke Kenneth Casso... | stack of changes to MultiCompUnit to speed it up |
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2021-12-01 |
Luke Kenneth Casso... | FunctionUnitBaseMulti which derives from ReservationSta... |
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2021-12-01 |
Luke Kenneth Casso... | better name for read latch in core.py |
tree | commitdiff |
2021-12-01 |
Luke Kenneth Casso... | remove redundant / mis-named variable in core |
tree | commitdiff |
2021-12-01 |
Luke Kenneth Casso... | code-comments |
tree | commitdiff |
2021-12-01 |
Luke Kenneth Casso... | remove unneeded data structure in core |
tree | commitdiff |
2021-12-01 |
Luke Kenneth Casso... | whoops treereduce on write-vector set/clr error |
tree | commitdiff |
2021-12-01 |
Luke Kenneth Casso... | more code-cleanup |
tree | commitdiff |
2021-12-01 |
Luke Kenneth Casso... | use new regspec_decode and fu.get_iospec functions |
tree | commitdiff |
2021-12-01 |
Luke Kenneth Casso... | core tidyup |
tree | commitdiff |
2021-11-30 |
Luke Kenneth Casso... | start allocating more FUs (more ReservationStations) |
tree | commitdiff |
2021-11-30 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2021-11-30 |
Luke Kenneth Casso... | add LogicalTestCases back in to test_core.py (pass) |
tree | commitdiff |
2021-11-30 |
Luke Kenneth Casso... | let PowerDecode2 decide which operand class to use... |
tree | commitdiff |
2021-11-30 |
Luke Kenneth Casso... | use latched readflag (recspec_decode_read "ok") instead... |
tree | commitdiff |
2021-11-30 |
Luke Kenneth Casso... | tidyup on read-flag latches |
tree | commitdiff |
2021-11-30 |
Luke Kenneth Casso... | fix read-decode information by latching not just the... |
tree | commitdiff |
2021-11-30 |
Luke Kenneth Casso... | fix write-after-write hazard checking |
tree | commitdiff |
2021-11-30 |
Luke Kenneth Casso... | allow busy to settle before checking state in test_core.py |
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2021-11-30 |
Luke Kenneth Casso... | only check regs right at the end in test_core.py overla... |
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2021-11-30 |
Luke Kenneth Casso... | move sim call before core run in test_core.py |
tree | commitdiff |
2021-11-30 |
Luke Kenneth Casso... | getting formerly unused test_core.py operational |
tree | commitdiff |
2021-11-29 |
Luke Kenneth Casso... | whoops missed make_hazard_vec test |
tree | commitdiff |
2021-11-29 |
Luke Kenneth Casso... | whoops do the set/get of the write-vector at a single... |
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