2022-01-03 |
Luke Kenneth Casso... | adding an extra option to issuer_verilog.py to be able... |
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2022-01-03 |
Luke Kenneth Casso... | bring external irq out for microwatt-compatible mode... |
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2022-01-03 |
Luke Kenneth Casso... | stop display of LDSTCompUnit debug info on every cycle |
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2022-01-03 |
Cesar Strauss | On inorder.py, after Execute, update the PC and go... |
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2021-12-30 |
Luke Kenneth Casso... | rename nia to cia in MMU input record and mmu FSM |
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2021-12-28 |
Cesar Strauss | Add an --inorder option to test_issuer.py |
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2021-12-28 |
Luke Kenneth Casso... | add misaligned mmu.bin test 5 notes: currently LoadStor... |
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2021-12-27 |
Luke Kenneth Casso... | found bug in mmu with calculating addrsh, should have... |
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2021-12-27 |
Luke Kenneth Casso... | add mmu.py microwatt mmu.bin test4 page table |
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2021-12-27 |
Cesar Strauss | Fix indentation |
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2021-12-26 |
Luke Kenneth Casso... | good grief, finally tracked down a piece of missing... |
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2021-12-26 |
Luke Kenneth Casso... | whoops, using variable RegStage0 in dcache stage_0... |
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2021-12-26 |
Luke Kenneth Casso... | missed reset of d_valid in dcache.py and missed that its |
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2021-12-26 |
Luke Kenneth Casso... | rename addr to raddr in LoadStore1 to avoid conflict... |
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2021-12-25 |
Luke Kenneth Casso... | add mmu.bin test2 to much simpler test_loadstore1.py |
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2021-12-25 |
Luke Kenneth Casso... | move msr in test_loadstore1.py outside of conditional... |
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2021-12-25 |
Luke Kenneth Casso... | whitespace |
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2021-12-25 |
Luke Kenneth Casso... | move microwatt mmu.bin test 3 page table to test pageta... |
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2021-12-25 |
Luke Kenneth Casso... | wait for MMU "done" when setting PRTBL and PIDR |
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2021-12-25 |
Luke Kenneth Casso... | add microwatt mmu.bin regression test test_mmu_3 |
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2021-12-24 |
Luke Kenneth Casso... | enable instruction redirect in mmu ifetch test |
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2021-12-23 |
Luke Kenneth Casso... | somehow managed to miss out setting r1.forward_valid1... |
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2021-12-23 |
Luke Kenneth Casso... | uniquify names in dcache.py |
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2021-12-23 |
Luke Kenneth Casso... | allow MSR reset to default to a value set by issuer_ver... |
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2021-12-23 |
Luke Kenneth Casso... | pass in msr_reset to issuer_verilog.py |
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2021-12-23 |
Luke Kenneth Casso... | add ability to set the reset values of RegFileArray |
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2021-12-23 |
Cesar Strauss | Remove extra wait on core_stop_o at end of Execute. |
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2021-12-23 |
Cesar Strauss | Re-enable core stopped signal when stopped. |
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2021-12-22 |
Luke Kenneth Casso... | only use a single variable for ack adjusting in dcache.py |
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2021-12-22 |
Luke Kenneth Casso... | fix issues with running core in DMI "stopped" status... |
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2021-12-22 |
Luke Kenneth Casso... | when setting DSISR in LoadStore1 use correct load bit... |
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2021-12-22 |
Luke Kenneth Casso... | use correct X-Form L field in OP_MTMSRD |
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2021-12-22 |
Luke Kenneth Casso... | check problem state in OP_MTMSRD from original reg... |
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2021-12-22 |
Luke Kenneth Casso... | whoops, use MSR.IR for I-Cache fetch! |
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2021-12-22 |
Luke Kenneth Casso... | remove unneeded state in LoadStore1 |
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2021-12-22 |
Luke Kenneth Casso... | clear instruction fault on exception WAIT_MMU ACK in... |
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2021-12-22 |
Luke Kenneth Casso... | clear out instr_fault when exception is thrown |
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2021-12-22 |
Luke Kenneth Casso... | clear instruction fault on idle/valid in Loadstore1 |
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2021-12-22 |
Luke Kenneth Casso... | ooo far too late at night to be doing this |
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2021-12-22 |
Luke Kenneth Casso... | whoops use C not Const |
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2021-12-22 |
Luke Kenneth Casso... | whoops use C not Const |
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2021-12-22 |
Luke Kenneth Casso... | remove bus_ack (found bug in Simulation, sorted) |
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2021-12-22 |
Luke Kenneth Casso... | bug in mmu setting radix tree size with one extra bit |
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2021-12-21 |
Luke Kenneth Casso... | continue to assert PC in FetchFSM if needed |
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2021-12-21 |
Luke Kenneth Casso... | enable I-Cache wishbone memory type in issuer_verilog... |
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2021-12-21 |
Luke Kenneth Casso... | whoops issuer_verilog.py enabling mmu has to pass micro... |
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2021-12-21 |
Luke Kenneth Casso... | for each unit test case in test_issuer_mmu_data_path... |
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2021-12-21 |
Luke Kenneth Casso... | test_issuer_mmu_data_path.py needs to use wb_get because of |
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2021-12-21 |
Luke Kenneth Casso... | mmu code-comments |
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2021-12-21 |
Luke Kenneth Casso... | comments |
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2021-12-21 |
Luke Kenneth Casso... | use prtbl in proc_tbl_wait in mmu |
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2021-12-21 |
Luke Kenneth Casso... | mmu.py comments |
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2021-12-20 |
Luke Kenneth Casso... | set up DAR correctly in unit tests, added set_ldst_spr... |
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2021-12-20 |
Luke Kenneth Casso... | unit tests for SPRs when MMU enabled, |
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2021-12-20 |
Luke Kenneth Casso... | more code-comments |
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2021-12-20 |
Luke Kenneth Casso... | code-comments in MMU |
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2021-12-20 |
Luke Kenneth Casso... | prefer not to invert when doing if/else. |
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2021-12-20 |
Luke Kenneth Casso... | more code-comments |
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2021-12-20 |
Luke Kenneth Casso... | add RTPDE - Radit Tree Page Directory Entry - Record... |
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2021-12-20 |
Luke Kenneth Casso... | add (and ues) PRTBL Record in MMU |
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2021-12-20 |
Luke Kenneth Casso... | create PGTBL Record and use it in MMU page_table_idle |
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2021-12-19 |
Luke Kenneth Casso... | add hard stop address in ifetch unit test, bit of a... |
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2021-12-19 |
Luke Kenneth Casso... | set terminate if core terminate requested |
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2021-12-19 |
Luke Kenneth Casso... | code-comments |
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2021-12-19 |
Luke Kenneth Casso... | add DMI STOPADDR register and use it in HDLRunner to... |
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2021-12-19 |
Luke Kenneth Casso... | break out when core is stopped in HDLRunner |
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2021-12-18 |
Luke Kenneth Casso... | add link to XICS bugreport |
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2021-12-18 |
Luke Kenneth Casso... | sort out reset signalling after tracking down Simulatio... |
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2021-12-18 |
Luke Kenneth Casso... | add icache/dcache/mmu unit test for TestIssuer |
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2021-12-18 |
Luke Kenneth Casso... | get instructions to re-run in issuer after I-Cache... |
tree | commitdiff |
2021-12-18 |
Luke Kenneth Casso... | forgot to connect up I-Cache to MMU |
tree | commitdiff |
2021-12-18 |
Luke Kenneth Casso... | move connection of bus.stall in icache.py, |
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2021-12-18 |
Luke Kenneth Casso... | tidyup |
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2021-12-18 |
Luke Kenneth Casso... | tlb_req_index is TLB_BITS long not TLB_SIZE |
tree | commitdiff |
2021-12-16 |
Luke Kenneth Casso... | whoops, a Simulation bug, dcache bus ack Signal needed... |
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2021-12-16 |
Luke Kenneth Casso... | give names to MMU records |
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2021-12-16 |
Luke Kenneth Casso... | set_mmu_spr was using the slow-SPR index for the regfile |
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2021-12-16 |
Luke Kenneth Casso... | whoops remove duplicate code (cut/paste error) no harm... |
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2021-12-15 |
Luke Kenneth Casso... | remove more unneeded code |
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2021-12-15 |
Luke Kenneth Casso... | read MSR.PR and MSR.DR and update ICache priv/virt... |
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2021-12-15 |
Luke Kenneth Casso... | remove more of SVP64 from TestIssuerInternalInOrder |
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2021-12-15 |
Luke Kenneth Casso... | remove update of pc, msr and svstate from TestIssuerInOrder |
tree | commitdiff |
2021-12-15 |
Luke Kenneth Casso... | move update of pc, msr and svstate into TestIssuerBase |
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2021-12-15 |
Luke Kenneth Casso... | comment-out TestIssuerInternalInorder for now |
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2021-12-15 |
Luke Kenneth Casso... | move alternative TestIssuerInternalInOrder to new file |
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2021-12-15 |
Luke Kenneth Casso... | split out common elaboratable code from TestIssuer, |
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2021-12-15 |
Luke Kenneth Casso... | big split-out of common functions in TestIssuer to... |
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2021-12-15 |
Luke Kenneth Casso... | simplifying / tidyup of TestIssuer to get CoreState |
tree | commitdiff |
2021-12-15 |
Luke Kenneth Casso... | sort out MSR, read/write in same way as PC/SVSTATE... |
tree | commitdiff |
2021-12-15 |
Luke Kenneth Casso... | whoops accidentally commented out setup of instructions |
tree | commitdiff |
2021-12-15 |
Luke Kenneth Casso... | get fetch_failed working with no MMU |
tree | commitdiff |
2021-12-14 |
Tobias Platen | test_loadstore1.py: test_loadstore1_ifetch_multi now... |
tree | commitdiff |
2021-12-14 |
Luke Kenneth Casso... | trying to get TestIssuer FSM to respond correctly to... |
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2021-12-14 |
Luke Kenneth Casso... | get OP_FETCH_FAILED to respond/return an exception... |
tree | commitdiff |
2021-12-14 |
Luke Kenneth Casso... | update wb_get memory with instructions if required |
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2021-12-14 |
Tobias Platen | fix test_loadstore1_ifetch_multi() in test_loadstore1.py |
tree | commitdiff |
2021-12-14 |
Tobias Platen | wip test case for virtual address fetch using fetch... |
tree | commitdiff |
2021-12-14 |
Tobias Platen | fix test_loadstore1_ifetch_multi() |
tree | commitdiff |
2021-12-14 |
Luke Kenneth Casso... | MMU LOOKUP for fetch failed, priv mode is inversion... |
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2021-12-14 |
Luke Kenneth Casso... | link MSR.PR into MMU FSM OP_FETCH_FAILED |
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