soc.git
2 years agomissed setting of r0_full to zero in dcache. not encountered as
Luke Kenneth Casson Leighton [Sat, 22 Jan 2022 15:19:00 +0000 (15:19 +0000)]
missed setting of r0_full to zero in dcache. not encountered as
a bug but would have done in future

2 years agoskip ilang data in branch test_pipe_caller.py
Luke Kenneth Casson Leighton [Fri, 21 Jan 2022 19:26:07 +0000 (19:26 +0000)]
skip ilang data in branch test_pipe_caller.py

2 years agoattempting to get compunit and test_pipe_caller unit tests
Luke Kenneth Casson Leighton [Fri, 21 Jan 2022 19:21:57 +0000 (19:21 +0000)]
attempting to get compunit and test_pipe_caller unit tests
up and running again.
grrr

2 years agosigh, monitor DEC/TB StateRegs "properly" so that the Issuer DEC/TB FSM
Luke Kenneth Casson Leighton [Fri, 21 Jan 2022 00:12:39 +0000 (00:12 +0000)]
sigh, monitor DEC/TB StateRegs "properly" so that the Issuer DEC/TB FSM
does not end up in a race condition with the SPR pipeline for writing
to DEC or TB

2 years agowhoops fix bug in setting of DEC/TB (State) in test_core.py
Luke Kenneth Casson Leighton [Fri, 21 Jan 2022 00:11:53 +0000 (00:11 +0000)]
whoops fix bug in setting of DEC/TB (State) in test_core.py

2 years agowhoops MFSPR DEC/TB was reading from FastRegs not StateRegs
Luke Kenneth Casson Leighton [Thu, 20 Jan 2022 18:38:20 +0000 (18:38 +0000)]
whoops MFSPR DEC/TB was reading from FastRegs not StateRegs
also TBU

2 years agowhoops forgot to enable fast-reg read in DMI
Luke Kenneth Casson Leighton [Wed, 19 Jan 2022 17:46:13 +0000 (17:46 +0000)]
whoops forgot to enable fast-reg read in DMI

2 years agoISI (0x400) trap is the only one that puts memory-based exception
Luke Kenneth Casson Leighton [Wed, 19 Jan 2022 17:18:35 +0000 (17:18 +0000)]
ISI (0x400) trap is the only one that puts memory-based exception
info into SRR1, not *all* memory-based exceptions

2 years agocomments
Luke Kenneth Casson Leighton [Wed, 19 Jan 2022 17:17:40 +0000 (17:17 +0000)]
comments

2 years agomove DEC and TB into StateRegs, to make room in FastRegs
Luke Kenneth Casson Leighton [Wed, 19 Jan 2022 12:16:25 +0000 (12:16 +0000)]
move DEC and TB into StateRegs, to make room in FastRegs
also has the advantage that DEC and TB could generate an accurate interrupt

2 years agoadd support for DMI debug read of FAST Regfile SPRs
Luke Kenneth Casson Leighton [Tue, 18 Jan 2022 18:15:17 +0000 (18:15 +0000)]
add support for DMI debug read of FAST Regfile SPRs
this to be able to do a side-by-side compare against microwatt
single-stepping

2 years agocomments on SRR1 in trap
Luke Kenneth Casson Leighton [Tue, 18 Jan 2022 16:28:49 +0000 (16:28 +0000)]
comments on SRR1 in trap

2 years agopreserve bits of SRR1 on a TRAP (including all interrupts) which in
Luke Kenneth Casson Leighton [Tue, 18 Jan 2022 13:42:12 +0000 (13:42 +0000)]
preserve bits of SRR1 on a TRAP (including all interrupts) which in
turn means that PowerDecoder2 has to read SRR1

2 years agofix hrfid and mtmsrd so that it is identical to microwatt
Luke Kenneth Casson Leighton [Mon, 17 Jan 2022 18:00:52 +0000 (18:00 +0000)]
fix hrfid and mtmsrd so that it is identical to microwatt
both allow MSR.ME to be set, which walks linux-5.7 along a different
codepath particularly for 0x900 exception handling

2 years agoconnect up DEC/TB FSM pauser from core to Issuer
Luke Kenneth Casson Leighton [Mon, 17 Jan 2022 17:59:59 +0000 (17:59 +0000)]
connect up DEC/TB FSM pauser from core to Issuer

2 years agocomments
Luke Kenneth Casson Leighton [Mon, 17 Jan 2022 12:01:17 +0000 (12:01 +0000)]
comments

2 years agowhitespace
Luke Kenneth Casson Leighton [Mon, 17 Jan 2022 12:00:36 +0000 (12:00 +0000)]
whitespace

2 years agoadd pause_dec_tb signal (not very sophisticated) to Core
Luke Kenneth Casson Leighton [Mon, 17 Jan 2022 11:59:56 +0000 (11:59 +0000)]
add pause_dec_tb signal (not very sophisticated) to Core
TODO, detect MTSPR and DEC/TB SPR being written to, but for now just
detect an entire SPR pipeline

2 years agoadd signal for pausing the DEC/TB FSM to IssuerBase
Luke Kenneth Casson Leighton [Mon, 17 Jan 2022 11:50:50 +0000 (11:50 +0000)]
add signal for pausing the DEC/TB FSM to IssuerBase
there is a potential issue with the DEC SPR that needs solving,
and there is a race condition where an mtspr DEC/TB could get
overwritten
adding a "pause" mechanism to the FSM should solve that

2 years agoraise interrupt on misaligned atomic LDST
Luke Kenneth Casson Leighton [Sun, 16 Jan 2022 16:29:13 +0000 (16:29 +0000)]
raise interrupt on misaligned atomic LDST

2 years agopass over store_done correctly from dcache over PortInterface
Luke Kenneth Casson Leighton [Sun, 16 Jan 2022 16:28:49 +0000 (16:28 +0000)]
pass over store_done correctly from dcache over PortInterface
into LDSTCompUnit so that it can set CR0 correctly on stdcx. etc.

2 years agoadd CR0 to LDSTCompUnit, for reporting if LR/SC store is done
Luke Kenneth Casson Leighton [Sun, 16 Jan 2022 09:08:52 +0000 (09:08 +0000)]
add CR0 to LDSTCompUnit, for reporting if LR/SC store is done

2 years agoremove PortInterface mmu_done signal,
Luke Kenneth Casson Leighton [Sun, 16 Jan 2022 08:54:22 +0000 (08:54 +0000)]
remove PortInterface mmu_done signal,
add store_done

2 years agoforgot name on dcache Reservation
Luke Kenneth Casson Leighton [Sat, 15 Jan 2022 21:47:18 +0000 (21:47 +0000)]
forgot name on dcache Reservation

2 years agopass over atomic signals to dcache from loadstore.
Luke Kenneth Casson Leighton [Sat, 15 Jan 2022 20:56:35 +0000 (20:56 +0000)]
pass over atomic signals to dcache from loadstore.
does not do everything yet: load-quad for example is not included

2 years agotry using req.op in RELOAD_WAIT_ACK to detect whether request
Luke Kenneth Casson Leighton [Sat, 15 Jan 2022 18:44:24 +0000 (18:44 +0000)]
try using req.op in RELOAD_WAIT_ACK to detect whether request
can complete next cycle

2 years agopass atomic reserve through from PortInterface to DCache
Luke Kenneth Casson Leighton [Sat, 15 Jan 2022 14:21:50 +0000 (14:21 +0000)]
pass atomic reserve through from PortInterface to DCache
not yet doing anything with it, so should be fine

2 years agoadd atomic LR/SC signal to LDSTCompUnit
Luke Kenneth Casson Leighton [Sat, 15 Jan 2022 14:06:44 +0000 (14:06 +0000)]
add atomic LR/SC signal to LDSTCompUnit

2 years agoadd reserve (atomic) signal to LDST data structures including PortInterface
Luke Kenneth Casson Leighton [Sat, 15 Jan 2022 14:04:55 +0000 (14:04 +0000)]
add reserve (atomic) signal to LDST data structures including PortInterface

2 years agotidyup PortInterface
Luke Kenneth Casson Leighton [Sat, 15 Jan 2022 14:03:02 +0000 (14:03 +0000)]
tidyup PortInterface

2 years agoworkaround for bug in dcache where the r1.req waiting to be deployed ldst_misalign
Luke Kenneth Casson Leighton [Sat, 15 Jan 2022 12:36:52 +0000 (12:36 +0000)]
workaround for bug in dcache where the r1.req waiting to be deployed
was interfering with the current state being executed
http://lists.libre-soc.org/pipermail/libre-soc-dev/2022-January/004358.html

2 years agoenable both linux-5.7 tests
Luke Kenneth Casson Leighton [Sat, 15 Jan 2022 12:35:12 +0000 (12:35 +0000)]
enable both linux-5.7 tests

2 years agosplit out CacheTag Record to separate structure
Luke Kenneth Casson Leighton [Fri, 14 Jan 2022 14:02:19 +0000 (14:02 +0000)]
split out CacheTag Record to separate structure

2 years agoupdate how d_valid is handled
Luke Kenneth Casson Leighton [Fri, 14 Jan 2022 03:02:39 +0000 (03:02 +0000)]
update how d_valid is handled

2 years agomissed setting r1.store_way and r1.store_row in STORE_WAIT_ACK state
Luke Kenneth Casson Leighton [Fri, 14 Jan 2022 01:42:07 +0000 (01:42 +0000)]
missed setting r1.store_way and r1.store_row in STORE_WAIT_ACK state

2 years agoRevert "dcache 2nd stage (r1) should only indicate not-busy"
Luke Kenneth Casson Leighton [Fri, 14 Jan 2022 01:28:17 +0000 (01:28 +0000)]
Revert "dcache 2nd stage (r1) should only indicate not-busy"

This reverts commit a03aefb1e8ae7d6110a328b57f1336890ebee469.

2 years agosecond test for linux-5.7
Luke Kenneth Casson Leighton [Fri, 14 Jan 2022 01:27:09 +0000 (01:27 +0000)]
second test for linux-5.7

2 years agoadd allow-overlap option to issuer_verilog.py
Luke Kenneth Casson Leighton [Wed, 12 Jan 2022 20:09:03 +0000 (20:09 +0000)]
add allow-overlap option to issuer_verilog.py

2 years agodcache 2nd stage (r1) should only indicate not-busy
Luke Kenneth Casson Leighton [Wed, 12 Jan 2022 12:11:12 +0000 (12:11 +0000)]
dcache 2nd stage (r1) should only indicate not-busy
(r1.full) when all the ACKs of a cache-line fill have been processed
doing this too early results in r0 being pushed into r1 whilst
ACKs are still outstanding, and their completion corrupts the
operation that should not have been put into r1 in the first place

2 years agofix issue with priv_mode not being passed correctly to MMU
Luke Kenneth Casson Leighton [Wed, 12 Jan 2022 11:22:24 +0000 (11:22 +0000)]
fix issue with priv_mode not being passed correctly to MMU
on instruction load

2 years agofix issue with d_valid in dcache, was not being set properly
Luke Kenneth Casson Leighton [Wed, 12 Jan 2022 11:21:40 +0000 (11:21 +0000)]
fix issue with d_valid in dcache, was not being set properly

2 years agoLoadStore1 priv_mode was not being correctly picked up by the MMU
Luke Kenneth Casson Leighton [Mon, 10 Jan 2022 23:03:25 +0000 (23:03 +0000)]
LoadStore1 priv_mode was not being correctly picked up by the MMU
priv_mode needs to come from the original LD/ST request (or the
fetch), which was not happening

2 years agograb the LDST request address for microwatt verilator debug purposes
Luke Kenneth Casson Leighton [Sun, 9 Jan 2022 23:40:34 +0000 (23:40 +0000)]
grab the LDST request address for microwatt verilator debug purposes

2 years agoadd linux-5.7 unit test which showed a silly error:
Luke Kenneth Casson Leighton [Sun, 9 Jan 2022 23:29:10 +0000 (23:29 +0000)]
add linux-5.7 unit test which showed a silly error:
LDST requests through PortInterface were truncated to 48 bits,
where linux uses the top 2 bits of an address for VM/guest (Quadrant 0-3)

2 years agofix MMU lookup after 2nd request (misaligned) by also updating the
Luke Kenneth Casson Leighton [Sat, 8 Jan 2022 17:46:56 +0000 (17:46 +0000)]
fix MMU lookup after 2nd request (misaligned) by also updating the
ldst_r with the next address/byte_sel

2 years agoadd microwatt mmu.bin test5 to show page-fault on misaligned LD
Luke Kenneth Casson Leighton [Sat, 8 Jan 2022 17:27:42 +0000 (17:27 +0000)]
add microwatt mmu.bin test5 to show page-fault on misaligned LD

2 years agodo not clear out ldst request after TLB entry is added
Luke Kenneth Casson Leighton [Sat, 8 Jan 2022 16:49:27 +0000 (16:49 +0000)]
do not clear out ldst request after TLB entry is added

2 years agoenable microwatt mmu test2
Luke Kenneth Casson Leighton [Sat, 8 Jan 2022 15:42:58 +0000 (15:42 +0000)]
enable microwatt mmu test2

2 years agowhitespace and use exc is None not exc == None
Luke Kenneth Casson Leighton [Sat, 8 Jan 2022 15:41:32 +0000 (15:41 +0000)]
whitespace and use exc is None not exc == None

2 years agoadd a second LD request to dcache which is merged with first,
Luke Kenneth Casson Leighton [Sat, 8 Jan 2022 15:26:03 +0000 (15:26 +0000)]
add a second LD request to dcache which is merged with first,
to implement mis-aligned LD operations

2 years agostart adding in mis-aligned LD/ST support into LoadStore1
Luke Kenneth Casson Leighton [Sat, 8 Jan 2022 14:10:16 +0000 (14:10 +0000)]
start adding in mis-aligned LD/ST support into LoadStore1
currently not activated or used so will have no effect

2 years agoadd function test_pi_ld_misalign
Tobias Platen [Sat, 8 Jan 2022 13:30:25 +0000 (14:30 +0100)]
add function test_pi_ld_misalign

2 years agobegin testcase for misalign
Tobias Platen [Fri, 7 Jan 2022 18:07:43 +0000 (19:07 +0100)]
begin testcase for misalign

2 years agowhitespace
Luke Kenneth Casson Leighton [Fri, 7 Jan 2022 16:59:59 +0000 (16:59 +0000)]
whitespace

2 years agoadd missing MSRSpec import
Luke Kenneth Casson Leighton [Fri, 7 Jan 2022 16:57:56 +0000 (16:57 +0000)]
add missing MSRSpec import

2 years agoadd msr_o to issuer in microwatt_compat mode
Luke Kenneth Casson Leighton [Fri, 7 Jan 2022 12:26:45 +0000 (12:26 +0000)]
add msr_o to issuer in microwatt_compat mode

2 years agodouble the number of lines in the L1 D/I-Cache to match microwatt
Luke Kenneth Casson Leighton [Thu, 6 Jan 2022 17:32:46 +0000 (17:32 +0000)]
double the number of lines in the L1 D/I-Cache to match microwatt
early tests halved the number of lines so as to reduce the size of SRAMs
but the issue is that this is mis-matched against the microwatt.dts
device-tree file

2 years agoadd SECOND_REQ state to loadstore.py, not yet implemented
Luke Kenneth Casson Leighton [Thu, 6 Jan 2022 17:31:57 +0000 (17:31 +0000)]
add SECOND_REQ state to loadstore.py, not yet implemented

2 years agoadd easy-to-access debug reporting of instruction and PC
Luke Kenneth Casson Leighton [Wed, 5 Jan 2022 16:32:42 +0000 (16:32 +0000)]
add easy-to-access debug reporting of instruction and PC
for microwatt verilator

2 years agouse microwatt-specific PLRU due to bug in nmutil version
Luke Kenneth Casson Leighton [Wed, 5 Jan 2022 16:31:39 +0000 (16:31 +0000)]
use microwatt-specific PLRU due to bug in nmutil version
(needs investigating)

2 years agofix DriverConflict over MSR write in Issuer/Core by providing an
Luke Kenneth Casson Leighton [Tue, 4 Jan 2022 17:19:47 +0000 (17:19 +0000)]
fix DriverConflict over MSR write in Issuer/Core by providing an
extra write-port to StateRegs

2 years agoremove FetchFSM from TestIssuer (it served its purpose for creating
Luke Kenneth Casson Leighton [Tue, 4 Jan 2022 17:03:48 +0000 (17:03 +0000)]
remove FetchFSM from TestIssuer (it served its purpose for creating
the Inorder version)

2 years agodoh, bus-hack was the wrong way round. *output* the address with
Luke Kenneth Casson Leighton [Mon, 3 Jan 2022 23:37:28 +0000 (23:37 +0000)]
doh, bus-hack was the wrong way round. *output* the address with
3 extra LSBs at the front to fix the wishbone incompatibility

2 years agosigh, microwatts wishbone bus usage is non-wishbone-compliant:
Luke Kenneth Casson Leighton [Mon, 3 Jan 2022 23:28:13 +0000 (23:28 +0000)]
sigh, microwatts wishbone bus usage is non-wishbone-compliant:
the full address (including LSBs) is dropped onto the bus

2 years agosigh have to allow external clocks and reset mess even in microwatt-compat
Luke Kenneth Casson Leighton [Mon, 3 Jan 2022 22:33:39 +0000 (22:33 +0000)]
sigh have to allow external clocks and reset mess even in microwatt-compat
mode.  soc.vhdl still needs to be able to pull an external reset OR
DMI needs to be able to instruct the core to do it. hardly surprising

2 years agogive module appropriate top-level name in microwatt compat mode
Luke Kenneth Casson Leighton [Mon, 3 Jan 2022 22:10:17 +0000 (22:10 +0000)]
give module appropriate top-level name in microwatt compat mode

2 years agoadd missing ext_irq signal to testissuer in microwatt compat mode
Luke Kenneth Casson Leighton [Mon, 3 Jan 2022 22:09:56 +0000 (22:09 +0000)]
add missing ext_irq signal to testissuer in microwatt compat mode

2 years agoadding an extra option to issuer_verilog.py to be able to cteate a
Luke Kenneth Casson Leighton [Mon, 3 Jan 2022 19:55:53 +0000 (19:55 +0000)]
adding an extra option to issuer_verilog.py to be able to cteate a
microwatt-core-compatible verilog file.  it needs to be compatible
with this interface, such that microwatt.v can have TestIssuerInternal
dropped directly in place

module core_512_88be32b2ccc17aa9df4dd9526954b105d7825eba(clk,
rst, alt_reset, \wishbone_insn_in.dat , \wishbone_insn_in.ack ,
\wishbone_insn_in.stall , \wishbone_data_in.dat , \wishbone_data_in.ack ,
\wishbone_data_in.stall , dmi_addr, dmi_din, dmi_req, dmi_wr, ext_irq,
\wishbone_insn_out.adr , \wishbone_insn_out.dat , \wishbone_insn_out.sel ,
\wishbone_insn_out.cyc , \wishbone_insn_out.stb , \wishbone_insn_out.we ,
\wishbone_data_out.adr , \wishbone_data_out.dat , \wishbone_data_out.sel ,
\wishbone_data_out.cyc , \wishbone_data_out.stb , \wishbone_data_out.we ,
dmi_dout, dmi_ack, terminated_out);

2 years agobring external irq out for microwatt-compatible mode in testissuer
Luke Kenneth Casson Leighton [Mon, 3 Jan 2022 19:00:46 +0000 (19:00 +0000)]
bring external irq out for microwatt-compatible mode in testissuer

2 years agostop display of LDSTCompUnit debug info on every cycle
Luke Kenneth Casson Leighton [Mon, 3 Jan 2022 14:08:19 +0000 (14:08 +0000)]
stop display of LDSTCompUnit debug info on every cycle

2 years agoOn inorder.py, after Execute, update the PC and go back to Fetch
Cesar Strauss [Mon, 3 Jan 2022 13:02:34 +0000 (10:02 -0300)]
On inorder.py, after Execute, update the PC and go back to Fetch

When removing SVP64 from inorder.py, this code block must have
been deleted by mistake.

"python test_issuer.py nosvp64 --inorder" now completes successfully,
without going into an infinite loop.

2 years agorename nia to cia in MMU input record and mmu FSM
Luke Kenneth Casson Leighton [Thu, 30 Dec 2021 14:24:20 +0000 (14:24 +0000)]
rename nia to cia in MMU input record and mmu FSM
this gets the PC passed over when an instruction fault occurs in
MSR.IR=True mode.

previous tests were only working because the instructions started at 0x0000
and a full cache line was read by I-Cache.  tests greater than a cache
line would have failed

2 years agoAdd an --inorder option to test_issuer.py
Cesar Strauss [Tue, 28 Dec 2021 21:06:02 +0000 (18:06 -0300)]
Add an --inorder option to test_issuer.py

To use, add "--inorder" as the last option, before the test list
It's using the newly added pspec flag (see openpower-isa repo)

2 years agoadd misaligned mmu.bin test 5 notes: currently LoadStore1 does not
Luke Kenneth Casson Leighton [Tue, 28 Dec 2021 02:30:11 +0000 (02:30 +0000)]
add misaligned mmu.bin test 5 notes: currently LoadStore1 does not
support misaligned LD/ST therefore a 0x600 exception is raised
where actually a page-table lookup over the boundary (into a second
PTE which does not exist) should result in a 0x300 (DAR) fault.

also took the opportunity to set align_intr when no-cache is requested
on dcbz

2 years agofound bug in mmu with calculating addrsh, should have been a right
Luke Kenneth Casson Leighton [Mon, 27 Dec 2021 18:52:05 +0000 (18:52 +0000)]
found bug in mmu with calculating addrsh, should have been a right
shift

2 years agoadd mmu.py microwatt mmu.bin test4 page table
Luke Kenneth Casson Leighton [Mon, 27 Dec 2021 18:51:28 +0000 (18:51 +0000)]
add mmu.py microwatt mmu.bin test4 page table
and add some debug / clarity for signal names in mmu.py
looking for addrsh bug

2 years agoFix indentation
Cesar Strauss [Mon, 27 Dec 2021 13:26:45 +0000 (10:26 -0300)]
Fix indentation

2 years agogood grief, finally tracked down a piece of missing code in the MMU
Luke Kenneth Casson Leighton [Sun, 26 Dec 2021 18:52:29 +0000 (18:52 +0000)]
good grief, finally tracked down a piece of missing code in the MMU
address-shift had somehow not been included
@@ -509,6 +523,10 @@ class MMU(Elaboratable):
         comb += tlb_mask.shift.eq(r.shift)
         comb += finalmask.eq(tlb_mask.mask)

+        # Shift address bits 61--12 right by 0--47 bits and
+        # supply the least significant 16 bits of the result.
+        comb += addrsh.eq(r.addr[12:62] << r.shift)
+

microwatt mmu.bin test 2 should now succeed

2 years agowhoops, using variable RegStage0 in dcache stage_0, should not use sync
Luke Kenneth Casson Leighton [Sun, 26 Dec 2021 00:43:31 +0000 (00:43 +0000)]
whoops, using variable RegStage0 in dcache stage_0, should not use sync

2 years agomissed reset of d_valid in dcache.py and missed that its
Luke Kenneth Casson Leighton [Sun, 26 Dec 2021 00:16:53 +0000 (00:16 +0000)]
missed reset of d_valid in dcache.py and missed that its
input is sync not comb

2 years agorename addr to raddr in LoadStore1 to avoid conflict with
Luke Kenneth Casson Leighton [Sun, 26 Dec 2021 00:15:35 +0000 (00:15 +0000)]
rename addr to raddr in LoadStore1 to avoid conflict with
PortInterfaceBase

2 years agoadd mmu.bin test2 to much simpler test_loadstore1.py
Luke Kenneth Casson Leighton [Sat, 25 Dec 2021 15:49:25 +0000 (15:49 +0000)]
add mmu.bin test2 to much simpler test_loadstore1.py
this eliminates TestIssuer (and the MMU FSM-based FU) from enquiries
into a VM lookup bug where virtual address is being treated as the real

2 years agomove msr in test_loadstore1.py outside of conditional block
Luke Kenneth Casson Leighton [Sat, 25 Dec 2021 15:42:04 +0000 (15:42 +0000)]
move msr in test_loadstore1.py outside of conditional block

2 years agowhitespace
Luke Kenneth Casson Leighton [Sat, 25 Dec 2021 15:32:59 +0000 (15:32 +0000)]
whitespace

2 years agomove microwatt mmu.bin test 3 page table to test pagetables module
Luke Kenneth Casson Leighton [Sat, 25 Dec 2021 15:27:20 +0000 (15:27 +0000)]
move microwatt mmu.bin test 3 page table to test pagetables module

2 years agowait for MMU "done" when setting PRTBL and PIDR
Luke Kenneth Casson Leighton [Sat, 25 Dec 2021 07:24:11 +0000 (07:24 +0000)]
wait for MMU "done" when setting PRTBL and PIDR

2 years agoadd microwatt mmu.bin regression test test_mmu_3
Luke Kenneth Casson Leighton [Sat, 25 Dec 2021 06:57:15 +0000 (06:57 +0000)]
add microwatt mmu.bin regression test test_mmu_3

2 years agoenable instruction redirect in mmu ifetch test
Luke Kenneth Casson Leighton [Fri, 24 Dec 2021 13:49:19 +0000 (13:49 +0000)]
enable instruction redirect in mmu ifetch test

2 years agosomehow managed to miss out setting r1.forward_valid1 in dcache
Luke Kenneth Casson Leighton [Thu, 23 Dec 2021 20:04:54 +0000 (20:04 +0000)]
somehow managed to miss out setting r1.forward_valid1 in dcache

2 years agouniquify names in dcache.py
Luke Kenneth Casson Leighton [Thu, 23 Dec 2021 19:47:39 +0000 (19:47 +0000)]
uniquify names in dcache.py

2 years agoallow MSR reset to default to a value set by issuer_verilog.py
Luke Kenneth Casson Leighton [Thu, 23 Dec 2021 17:05:53 +0000 (17:05 +0000)]
allow MSR reset to default to a value set by issuer_verilog.py

2 years agopass in msr_reset to issuer_verilog.py
Luke Kenneth Casson Leighton [Thu, 23 Dec 2021 16:57:59 +0000 (16:57 +0000)]
pass in msr_reset to issuer_verilog.py

2 years agoadd ability to set the reset values of RegFileArray
Luke Kenneth Casson Leighton [Thu, 23 Dec 2021 16:56:21 +0000 (16:56 +0000)]
add ability to set the reset values of RegFileArray

2 years agoRemove extra wait on core_stop_o at end of Execute.
Cesar Strauss [Thu, 23 Dec 2021 11:45:25 +0000 (08:45 -0300)]
Remove extra wait on core_stop_o at end of Execute.

Fixes https://bugs.libre-soc.org/show_bug.cgi?id=726
Now, there is only one wait, before Fetch.
It fixes DMI single-stepping for Power ISA 3.0B instructions, but
single-stepping in the middle of a SVP64 VL loop no longer works,
for now.

2 years agoRe-enable core stopped signal when stopped.
Cesar Strauss [Thu, 23 Dec 2021 10:56:42 +0000 (07:56 -0300)]
Re-enable core stopped signal when stopped.

2 years agoonly use a single variable for ack adjusting in dcache.py
Luke Kenneth Casson Leighton [Wed, 22 Dec 2021 23:21:50 +0000 (23:21 +0000)]
only use a single variable for ack adjusting in dcache.py
STORE_WAIT_ACK state

2 years agofix issues with running core in DMI "stopped" status when
Luke Kenneth Casson Leighton [Wed, 22 Dec 2021 23:20:14 +0000 (23:20 +0000)]
fix issues with running core in DMI "stopped" status when
issuing a single-step

2 years agowhen setting DSISR in LoadStore1 use correct load bit (from register)
Luke Kenneth Casson Leighton [Wed, 22 Dec 2021 03:53:45 +0000 (03:53 +0000)]
when setting DSISR in LoadStore1 use correct load bit (from register)

2 years agouse correct X-Form L field in OP_MTMSRD
Luke Kenneth Casson Leighton [Wed, 22 Dec 2021 03:53:13 +0000 (03:53 +0000)]
use correct X-Form L field in OP_MTMSRD

2 years agocheck problem state in OP_MTMSRD from original reg RA rather than
Luke Kenneth Casson Leighton [Wed, 22 Dec 2021 03:24:44 +0000 (03:24 +0000)]
check problem state in OP_MTMSRD from original reg RA rather than
after the fact