| 2022-01-25 |
Luke Kenneth... | LDSTException now passing bits of SRR1 around to the... |
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| 2022-01-24 |
Luke Kenneth... | comments |
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| 2022-01-24 |
Luke Kenneth... | hmm there seems to have been an error in DTLB Read, |
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| 2022-01-24 |
Luke Kenneth... | bool test on traptype to |
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| 2022-01-23 |
Luke Kenneth... | looked in soc.vhdl in microwatt and the parameters... |
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| 2022-01-23 |
Luke Kenneth... | add debug output of whether stall occurs on dcache |
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| 2022-01-22 |
Luke Kenneth... | missed setting of r0_full to zero in dcache. not encoun... |
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| 2022-01-21 |
Luke Kenneth... | skip ilang data in branch test_pipe_caller.py |
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| 2022-01-21 |
Luke Kenneth... | attempting to get compunit and test_pipe_caller unit... |
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| 2022-01-21 |
Luke Kenneth... | sigh, monitor DEC/TB StateRegs "properly" so that the... |
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| 2022-01-21 |
Luke Kenneth... | whoops fix bug in setting of DEC/TB (State) in test_core.py |
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| 2022-01-20 |
Luke Kenneth... | whoops MFSPR DEC/TB was reading from FastRegs not StateRegs |
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| 2022-01-19 |
Luke Kenneth... | whoops forgot to enable fast-reg read in DMI |
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| 2022-01-19 |
Luke Kenneth... | ISI (0x400) trap is the only one that puts memory-based... |
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| 2022-01-19 |
Luke Kenneth... | comments |
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| 2022-01-19 |
Luke Kenneth... | move DEC and TB into StateRegs, to make room in FastRegs |
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| 2022-01-18 |
Luke Kenneth... | add support for DMI debug read of FAST Regfile SPRs |
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| 2022-01-18 |
Luke Kenneth... | comments on SRR1 in trap |
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| 2022-01-18 |
Luke Kenneth... | preserve bits of SRR1 on a TRAP (including all interrup... |
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| 2022-01-17 |
Luke Kenneth... | fix hrfid and mtmsrd so that it is identical to microwatt |
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| 2022-01-17 |
Luke Kenneth... | connect up DEC/TB FSM pauser from core to Issuer |
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| 2022-01-17 |
Luke Kenneth... | comments |
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| 2022-01-17 |
Luke Kenneth... | whitespace |
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| 2022-01-17 |
Luke Kenneth... | add pause_dec_tb signal (not very sophisticated) to... |
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| 2022-01-17 |
Luke Kenneth... | add signal for pausing the DEC/TB FSM to IssuerBase |
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| 2022-01-16 |
Luke Kenneth... | raise interrupt on misaligned atomic LDST |
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| 2022-01-16 |
Luke Kenneth... | pass over store_done correctly from dcache over PortInt... |
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| 2022-01-16 |
Luke Kenneth... | add CR0 to LDSTCompUnit, for reporting if LR/SC store... |
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| 2022-01-16 |
Luke Kenneth... | remove PortInterface mmu_done signal, |
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| 2022-01-15 |
Luke Kenneth... | forgot name on dcache Reservation |
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| 2022-01-15 |
Luke Kenneth... | pass over atomic signals to dcache from loadstore. |
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| 2022-01-15 |
Luke Kenneth... | try using req.op in RELOAD_WAIT_ACK to detect whether... |
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| 2022-01-15 |
Luke Kenneth... | pass atomic reserve through from PortInterface to DCache |
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| 2022-01-15 |
Luke Kenneth... | add atomic LR/SC signal to LDSTCompUnit |
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| 2022-01-15 |
Luke Kenneth... | add reserve (atomic) signal to LDST data structures... |
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| 2022-01-15 |
Luke Kenneth... | tidyup PortInterface |
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| 2022-01-15 |
Luke Kenneth... | workaround for bug in dcache where the r1.req waiting... ldst_misalign |
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| 2022-01-15 |
Luke Kenneth... | enable both linux-5.7 tests |
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| 2022-01-14 |
Luke Kenneth... | split out CacheTag Record to separate structure |
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| 2022-01-14 |
Luke Kenneth... | update how d_valid is handled |
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| 2022-01-14 |
Luke Kenneth... | missed setting r1.store_way and r1.store_row in STORE_W... |
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| 2022-01-14 |
Luke Kenneth... | Revert "dcache 2nd stage (r1) should only indicate... |
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| 2022-01-14 |
Luke Kenneth... | second test for linux-5.7 |
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| 2022-01-12 |
Luke Kenneth... | add allow-overlap option to issuer_verilog.py |
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| 2022-01-12 |
Luke Kenneth... | dcache 2nd stage (r1) should only indicate not-busy |
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| 2022-01-12 |
Luke Kenneth... | fix issue with priv_mode not being passed correctly... |
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| 2022-01-12 |
Luke Kenneth... | fix issue with d_valid in dcache, was not being set... |
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| 2022-01-10 |
Luke Kenneth... | LoadStore1 priv_mode was not being correctly picked... |
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| 2022-01-09 |
Luke Kenneth... | grab the LDST request address for microwatt verilator... |
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| 2022-01-09 |
Luke Kenneth... | add linux-5.7 unit test which showed a silly error: |
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| 2022-01-08 |
Luke Kenneth... | fix MMU lookup after 2nd request (misaligned) by also... |
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| 2022-01-08 |
Luke Kenneth... | add microwatt mmu.bin test5 to show page-fault on misal... |
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| 2022-01-08 |
Luke Kenneth... | do not clear out ldst request after TLB entry is added |
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| 2022-01-08 |
Luke Kenneth... | enable microwatt mmu test2 |
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| 2022-01-08 |
Luke Kenneth... | whitespace and use exc is None not exc == None |
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| 2022-01-08 |
Luke Kenneth... | add a second LD request to dcache which is merged with... |
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| 2022-01-08 |
Luke Kenneth... | start adding in mis-aligned LD/ST support into LoadStore1 |
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| 2022-01-08 |
Tobias Platen | add function test_pi_ld_misalign |
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| 2022-01-07 |
Tobias Platen | begin testcase for misalign |
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| 2022-01-07 |
Luke Kenneth... | whitespace |
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| 2022-01-07 |
Luke Kenneth... | add missing MSRSpec import |
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| 2022-01-07 |
Luke Kenneth... | add msr_o to issuer in microwatt_compat mode |
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| 2022-01-06 |
Luke Kenneth... | double the number of lines in the L1 D/I-Cache to match... |
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| 2022-01-06 |
Luke Kenneth... | add SECOND_REQ state to loadstore.py, not yet implemented |
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| 2022-01-05 |
Luke Kenneth... | add easy-to-access debug reporting of instruction and PC |
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| 2022-01-05 |
Luke Kenneth... | use microwatt-specific PLRU due to bug in nmutil version |
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| 2022-01-04 |
Luke Kenneth... | fix DriverConflict over MSR write in Issuer/Core by... |
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| 2022-01-04 |
Luke Kenneth... | remove FetchFSM from TestIssuer (it served its purpose... |
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| 2022-01-03 |
Luke Kenneth... | doh, bus-hack was the wrong way round. *output* the... |
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| 2022-01-03 |
Luke Kenneth... | sigh, microwatts wishbone bus usage is non-wishbone... |
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| 2022-01-03 |
Luke Kenneth... | sigh have to allow external clocks and reset mess even... |
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| 2022-01-03 |
Luke Kenneth... | give module appropriate top-level name in microwatt... |
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| 2022-01-03 |
Luke Kenneth... | add missing ext_irq signal to testissuer in microwatt... |
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| 2022-01-03 |
Luke Kenneth... | adding an extra option to issuer_verilog.py to be able... |
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| 2022-01-03 |
Luke Kenneth... | bring external irq out for microwatt-compatible mode... |
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| 2022-01-03 |
Luke Kenneth... | stop display of LDSTCompUnit debug info on every cycle |
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| 2022-01-03 |
Cesar Strauss | On inorder.py, after Execute, update the PC and go... |
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| 2021-12-30 |
Luke Kenneth... | rename nia to cia in MMU input record and mmu FSM |
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| 2021-12-28 |
Cesar Strauss | Add an --inorder option to test_issuer.py |
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| 2021-12-28 |
Luke Kenneth... | add misaligned mmu.bin test 5 notes: currently LoadStor... |
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| 2021-12-27 |
Luke Kenneth... | found bug in mmu with calculating addrsh, should have... |
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| 2021-12-27 |
Luke Kenneth... | add mmu.py microwatt mmu.bin test4 page table |
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| 2021-12-27 |
Cesar Strauss | Fix indentation |
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| 2021-12-26 |
Luke Kenneth... | good grief, finally tracked down a piece of missing... |
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| 2021-12-26 |
Luke Kenneth... | whoops, using variable RegStage0 in dcache stage_0... |
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| 2021-12-26 |
Luke Kenneth... | missed reset of d_valid in dcache.py and missed that its |
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| 2021-12-26 |
Luke Kenneth... | rename addr to raddr in LoadStore1 to avoid conflict... |
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| 2021-12-25 |
Luke Kenneth... | add mmu.bin test2 to much simpler test_loadstore1.py |
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| 2021-12-25 |
Luke Kenneth... | move msr in test_loadstore1.py outside of conditional... |
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| 2021-12-25 |
Luke Kenneth... | whitespace |
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| 2021-12-25 |
Luke Kenneth... | move microwatt mmu.bin test 3 page table to test pageta... |
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| 2021-12-25 |
Luke Kenneth... | wait for MMU "done" when setting PRTBL and PIDR |
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| 2021-12-25 |
Luke Kenneth... | add microwatt mmu.bin regression test test_mmu_3 |
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| 2021-12-24 |
Luke Kenneth... | enable instruction redirect in mmu ifetch test |
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| 2021-12-23 |
Luke Kenneth... | somehow managed to miss out setting r1.forward_valid1... |
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| 2021-12-23 |
Luke Kenneth... | uniquify names in dcache.py |
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| 2021-12-23 |
Luke Kenneth... | allow MSR reset to default to a value set by issuer_ver... |
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| 2021-12-23 |
Luke Kenneth... | pass in msr_reset to issuer_verilog.py |
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| 2021-12-23 |
Luke Kenneth... | add ability to set the reset values of RegFileArray |
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| 2021-12-23 |
Cesar Strauss | Remove extra wait on core_stop_o at end of Execute. |
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