nope. put it back and connect to platform pads in LS180Platform
[soc.git] / src / soc / simple /
2020-10-03 Luke Kenneth Casso... minor reorg on JTAG, allow alternative pinset dict...
2020-10-01 Luke Kenneth Casso... add clksel, pll to ls180
2020-10-01 Luke Kenneth Casso... create dummy PLL block, connect up to core and clock...
2020-09-28 Luke Kenneth Casso... missing pspec
2020-09-28 Luke Kenneth Casso... add "nocore" option to build verilog
2020-09-28 Luke Kenneth Casso... switch off internal gpio (testing)
2020-09-26 Luke Kenneth Casso... DMI-to-JTAG needed to be "sync" to get ack/resp right
2020-09-26 Cesar StraussConvert a few more tests to be able to use cxxsim
2020-09-24 Cesar StraussUse nmutil simulator module to simplify choosing among...
2020-09-22 Luke Kenneth Casso... move dmi_sim to separate module
2020-09-22 Luke Kenneth Casso... add jtagremote to litex sim, add new "variant" to core...
2020-09-22 Luke Kenneth Casso... add jtag interface to issuer_verilog
2020-09-22 Luke Kenneth Casso... add MMU (commented out)
2020-09-19 Luke Kenneth Casso... remove the gpio peripheral which was previously hard...
2020-09-08 Luke Kenneth Casso... create a special subset of Decoder Record for storing...
2020-09-08 Luke Kenneth Casso... pass in state into PowerDecode2, save on eqs and wires
2020-09-08 Luke Kenneth Casso... give Decode2Execute1Type in core a name
2020-09-08 Luke Kenneth Casso... pass in CoreState to PowerDecoder rather than eq a...
2020-09-08 Luke Kenneth Casso... add cxxsim option
2020-09-07 Luke Kenneth Casso... use PowerDecoderSubsets for FUs, except for TRAP which...
2020-09-07 Luke Kenneth Casso... add per-FU PowerDecoders. should now be subsettable
2020-09-06 Luke Kenneth Casso... copy dec SPR into decoder cur_state
2020-09-06 Luke Kenneth Casso... wark-wark, fast regs is binary-addressed
2020-09-06 Luke Kenneth Casso... add comments for DEC / TB
2020-09-06 Luke Kenneth Casso... add a DEC/TB FSM to TestIssuer
2020-09-05 Luke Kenneth Casso... add comments on MSR read
2020-09-05 Luke Kenneth Casso... move GPIO IRQ to 15 to match microwatt modifications
2020-09-05 Luke Kenneth Casso... MSR read in INSN_READ only occurs for 1 cycle
2020-09-05 Luke Kenneth Casso... sync on ICP eint
2020-09-05 Luke Kenneth Casso... connect XICS core irq to Decode2 eint
2020-09-05 Luke Kenneth Casso... add simple GPIO wishbone bus to litex sim.py
2020-09-05 Luke Kenneth Casso... add simple GPIO peripheral to verilog TestIssuer
2020-09-04 Luke Kenneth Casso... bring out XICS ICS interrupt levels so that they can...
2020-09-04 Luke Kenneth Casso... adding option to include XICS external interrupts.
2020-08-30 Luke Kenneth Casso... reversal of FXM mask for one-hot selection in OP_MTCR...
2020-08-29 Luke Kenneth Casso... add XER read via DMI interface to sim.py
2020-08-29 Luke Kenneth Casso... add hack to get at XER through DMI interface
2020-08-27 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-27 Luke Kenneth Casso... overflow-enable does not occur on shift operations
2020-08-25 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-25 Luke Kenneth Casso... add CR read to DMI interface
2020-08-24 Luke Kenneth Casso... add isel CR tests to run on qemu (confirmed working)
2020-08-24 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-23 Luke Kenneth Casso... bring "core stopped" signal out through DMI interface
2020-08-21 Luke Kenneth Casso... testing 64-bit wishbone bus after 32-bit *still* fails...
2020-08-21 Luke Kenneth Casso... get litex sim enabled with 32-bit wishbone bus
2020-08-16 Luke Kenneth Casso... attempting to track down bug in litex bios memtest
2020-08-16 Luke Kenneth Casso... read delay on getting regfile data
2020-08-15 Luke Kenneth Casso... rather big change to interaction between regfile and...
2020-08-14 Luke Kenneth Casso... ha! "state" (pc, msr) not properly passed to core
2020-08-14 Luke Kenneth Casso... drop in insn_state synchronously in issuer, at same...
2020-08-14 Luke Kenneth Casso... finally, fix decoder combinatorial loop
2020-08-14 Luke Kenneth Casso... sync up the core decode-execute state,
2020-08-14 Luke Kenneth Casso... move instruction decoder out of core
2020-08-14 Luke Kenneth Casso... move regspec / rdflag decoding functions out of PowerDe...
2020-08-14 Luke Kenneth Casso... sort out instruction stop/cancel when adding a new...
2020-08-14 Luke Kenneth Casso... put multi-ports back (for read) on int and fast regfiles
2020-08-13 Luke Kenneth Casso... fix dmi reg read
2020-08-13 Luke Kenneth Casso... sync on pc writing when changed
2020-08-13 Luke Kenneth Casso... sync on read of regfile ports
2020-08-13 Luke Kenneth Casso... sigh. convert INT regfile to binary addressing
2020-08-11 Luke Kenneth Casso... sigh, remove yet another int regfile read port
2020-08-11 Luke Kenneth Casso... massive reduction in gate count by using alternative...
2020-08-11 Luke Kenneth Casso... reduce regfile port usage for INT and FAST
2020-08-11 Luke Kenneth Casso... prepare write ports to be shared
2020-08-11 Luke Kenneth Casso... move write regfile picker creation to new function
2020-08-11 Luke Kenneth Casso... reduce regfile ports by creating separate STATE regfile
2020-08-11 Luke Kenneth Casso... reducing regfile port usage by sharing read ports
2020-08-10 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-09 Luke Kenneth Casso... write pulse in issuer
2020-08-09 Luke Kenneth Casso... fix combinatorial loop in ldst compunit
2020-08-09 Luke Kenneth Casso... use rising edge detection on st go_i/rel_o
2020-08-09 Luke Kenneth Casso... add logical test issuer case
2020-08-09 Luke Kenneth Casso... get rid of MSR read combinatorial loop
2020-08-09 Luke Kenneth Casso... delay go_st by one cycle, break combinatorial loop
2020-08-05 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-05 Luke Kenneth Casso... add div test cases into test_issuer.py
2020-08-05 Luke Kenneth Casso... add div FSM as default for test_issuer in verilog and...
2020-08-04 Luke Kenneth Casso... read/set pc outside of FSM so that DMI interface can...
2020-08-04 Luke Kenneth Casso... whoops must output NIA not PC to debug DMI query in...
2020-08-04 Luke Kenneth Casso... allow instruction to run if initiated whilst "stopped...
2020-08-04 Luke Kenneth Casso... add DMI debug interface to libresoc litex sim
2020-08-03 Luke Kenneth Casso... add quick demo/test of reading DMI reg 9
2020-08-03 Luke Kenneth Casso... pass state (MSR/PC) around between PowerDecode2, DMI...
2020-08-03 Luke Kenneth Casso... use new soc.config.state CoreState class in DMI and...
2020-08-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-08-03 Luke Kenneth Casso... change over to DMI debug start/stop interface
2020-07-31 Luke Kenneth Casso... restrict external port list further in test_issuer
2020-07-30 Luke Kenneth Casso... core_start/stop/endian were inverted (output)
2020-07-30 Luke Kenneth Casso... ha! have to explicitly specify the ports when writing...
2020-07-29 Luke Kenneth Casso... bit of a big change: add prefixes "cu_" to all CompUnit...
2020-07-29 Jacob Lifshayadd __init__.py to all source directories
2020-07-29 Jacob Lifshayformat some tests
2020-07-26 Luke Kenneth Casso... add nop test cases
2020-07-26 Luke Kenneth Casso... activate some of new accumulator-based tests in test_issuer
2020-07-23 Luke Kenneth Casso... support 32-bit mem width setting
2020-07-23 Luke Kenneth Casso... allow imem to be 64/32 bit wide
2020-07-23 Luke Kenneth Casso... begin core in running state
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
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