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soc.git
2022-01-08 Luke Kenneth... add a second LD request to dcache which is merged with... commit | commitdiff | tree
2022-01-08 Luke Kenneth... start adding in mis-aligned LD/ST support into LoadStore1 commit | commitdiff | tree
2022-01-08 Tobias Platenadd function test_pi_ld_misalign commit | commitdiff | tree
2022-01-07 Tobias Platenbegin testcase for misalign commit | commitdiff | tree
2022-01-07 Luke Kenneth... whitespace commit | commitdiff | tree
2022-01-07 Luke Kenneth... add missing MSRSpec import commit | commitdiff | tree
2022-01-07 Luke Kenneth... add msr_o to issuer in microwatt_compat mode commit | commitdiff | tree
2022-01-06 Luke Kenneth... double the number of lines in the L1 D/I-Cache to match... commit | commitdiff | tree
2022-01-06 Luke Kenneth... add SECOND_REQ state to loadstore.py, not yet implemented commit | commitdiff | tree
2022-01-05 Luke Kenneth... add easy-to-access debug reporting of instruction and PC commit | commitdiff | tree
2022-01-05 Luke Kenneth... use microwatt-specific PLRU due to bug in nmutil version commit | commitdiff | tree
2022-01-04 Luke Kenneth... fix DriverConflict over MSR write in Issuer/Core by... commit | commitdiff | tree
2022-01-04 Luke Kenneth... remove FetchFSM from TestIssuer (it served its purpose... commit | commitdiff | tree
2022-01-03 Luke Kenneth... doh, bus-hack was the wrong way round. *output* the... commit | commitdiff | tree
2022-01-03 Luke Kenneth... sigh, microwatts wishbone bus usage is non-wishbone... commit | commitdiff | tree
2022-01-03 Luke Kenneth... sigh have to allow external clocks and reset mess even... commit | commitdiff | tree
2022-01-03 Luke Kenneth... give module appropriate top-level name in microwatt... commit | commitdiff | tree
2022-01-03 Luke Kenneth... add missing ext_irq signal to testissuer in microwatt... commit | commitdiff | tree
2022-01-03 Luke Kenneth... adding an extra option to issuer_verilog.py to be able... commit | commitdiff | tree
2022-01-03 Luke Kenneth... bring external irq out for microwatt-compatible mode... commit | commitdiff | tree
2022-01-03 Luke Kenneth... stop display of LDSTCompUnit debug info on every cycle commit | commitdiff | tree
2022-01-03 Cesar StraussOn inorder.py, after Execute, update the PC and go... commit | commitdiff | tree
2021-12-30 Luke Kenneth... rename nia to cia in MMU input record and mmu FSM commit | commitdiff | tree
2021-12-28 Cesar StraussAdd an --inorder option to test_issuer.py commit | commitdiff | tree
2021-12-28 Luke Kenneth... add misaligned mmu.bin test 5 notes: currently LoadStor... commit | commitdiff | tree
2021-12-27 Luke Kenneth... found bug in mmu with calculating addrsh, should have... commit | commitdiff | tree
2021-12-27 Luke Kenneth... add mmu.py microwatt mmu.bin test4 page table commit | commitdiff | tree
2021-12-27 Cesar StraussFix indentation commit | commitdiff | tree
2021-12-26 Luke Kenneth... good grief, finally tracked down a piece of missing... commit | commitdiff | tree
2021-12-26 Luke Kenneth... whoops, using variable RegStage0 in dcache stage_0... commit | commitdiff | tree
2021-12-26 Luke Kenneth... missed reset of d_valid in dcache.py and missed that its commit | commitdiff | tree
2021-12-26 Luke Kenneth... rename addr to raddr in LoadStore1 to avoid conflict... commit | commitdiff | tree
2021-12-25 Luke Kenneth... add mmu.bin test2 to much simpler test_loadstore1.py commit | commitdiff | tree
2021-12-25 Luke Kenneth... move msr in test_loadstore1.py outside of conditional... commit | commitdiff | tree
2021-12-25 Luke Kenneth... whitespace commit | commitdiff | tree
2021-12-25 Luke Kenneth... move microwatt mmu.bin test 3 page table to test pageta... commit | commitdiff | tree
2021-12-25 Luke Kenneth... wait for MMU "done" when setting PRTBL and PIDR commit | commitdiff | tree
2021-12-25 Luke Kenneth... add microwatt mmu.bin regression test test_mmu_3 commit | commitdiff | tree
2021-12-24 Luke Kenneth... enable instruction redirect in mmu ifetch test commit | commitdiff | tree
2021-12-23 Luke Kenneth... somehow managed to miss out setting r1.forward_valid1... commit | commitdiff | tree
2021-12-23 Luke Kenneth... uniquify names in dcache.py commit | commitdiff | tree
2021-12-23 Luke Kenneth... allow MSR reset to default to a value set by issuer_ver... commit | commitdiff | tree
2021-12-23 Luke Kenneth... pass in msr_reset to issuer_verilog.py commit | commitdiff | tree
2021-12-23 Luke Kenneth... add ability to set the reset values of RegFileArray commit | commitdiff | tree
2021-12-23 Cesar StraussRemove extra wait on core_stop_o at end of Execute. commit | commitdiff | tree
2021-12-23 Cesar StraussRe-enable core stopped signal when stopped. commit | commitdiff | tree
2021-12-22 Luke Kenneth... only use a single variable for ack adjusting in dcache.py commit | commitdiff | tree
2021-12-22 Luke Kenneth... fix issues with running core in DMI "stopped" status... commit | commitdiff | tree
2021-12-22 Luke Kenneth... when setting DSISR in LoadStore1 use correct load bit... commit | commitdiff | tree
2021-12-22 Luke Kenneth... use correct X-Form L field in OP_MTMSRD commit | commitdiff | tree
2021-12-22 Luke Kenneth... check problem state in OP_MTMSRD from original reg... commit | commitdiff | tree
2021-12-22 Luke Kenneth... whoops, use MSR.IR for I-Cache fetch! commit | commitdiff | tree
2021-12-22 Luke Kenneth... remove unneeded state in LoadStore1 commit | commitdiff | tree
2021-12-22 Luke Kenneth... clear instruction fault on exception WAIT_MMU ACK in... commit | commitdiff | tree
2021-12-22 Luke Kenneth... clear out instr_fault when exception is thrown commit | commitdiff | tree
2021-12-22 Luke Kenneth... clear instruction fault on idle/valid in Loadstore1 commit | commitdiff | tree
2021-12-22 Luke Kenneth... ooo far too late at night to be doing this commit | commitdiff | tree
2021-12-22 Luke Kenneth... whoops use C not Const commit | commitdiff | tree
2021-12-22 Luke Kenneth... whoops use C not Const commit | commitdiff | tree
2021-12-22 Luke Kenneth... remove bus_ack (found bug in Simulation, sorted) commit | commitdiff | tree
2021-12-22 Luke Kenneth... bug in mmu setting radix tree size with one extra bit commit | commitdiff | tree
2021-12-21 Luke Kenneth... continue to assert PC in FetchFSM if needed commit | commitdiff | tree
2021-12-21 Luke Kenneth... enable I-Cache wishbone memory type in issuer_verilog... commit | commitdiff | tree
2021-12-21 Luke Kenneth... whoops issuer_verilog.py enabling mmu has to pass micro... commit | commitdiff | tree
2021-12-21 Luke Kenneth... for each unit test case in test_issuer_mmu_data_path... commit | commitdiff | tree
2021-12-21 Luke Kenneth... test_issuer_mmu_data_path.py needs to use wb_get because of commit | commitdiff | tree
2021-12-21 Luke Kenneth... mmu code-comments commit | commitdiff | tree
2021-12-21 Luke Kenneth... comments commit | commitdiff | tree
2021-12-21 Luke Kenneth... use prtbl in proc_tbl_wait in mmu commit | commitdiff | tree
2021-12-21 Luke Kenneth... mmu.py comments commit | commitdiff | tree
2021-12-20 Luke Kenneth... set up DAR correctly in unit tests, added set_ldst_spr... commit | commitdiff | tree
2021-12-20 Luke Kenneth... unit tests for SPRs when MMU enabled, commit | commitdiff | tree
2021-12-20 Luke Kenneth... more code-comments commit | commitdiff | tree
2021-12-20 Luke Kenneth... code-comments in MMU commit | commitdiff | tree
2021-12-20 Luke Kenneth... prefer not to invert when doing if/else. commit | commitdiff | tree
2021-12-20 Luke Kenneth... more code-comments commit | commitdiff | tree
2021-12-20 Luke Kenneth... add RTPDE - Radit Tree Page Directory Entry - Record... commit | commitdiff | tree
2021-12-20 Luke Kenneth... add (and ues) PRTBL Record in MMU commit | commitdiff | tree
2021-12-20 Luke Kenneth... create PGTBL Record and use it in MMU page_table_idle commit | commitdiff | tree
2021-12-19 Luke Kenneth... add hard stop address in ifetch unit test, bit of a... commit | commitdiff | tree
2021-12-19 Luke Kenneth... set terminate if core terminate requested commit | commitdiff | tree
2021-12-19 Luke Kenneth... code-comments commit | commitdiff | tree
2021-12-19 Luke Kenneth... add DMI STOPADDR register and use it in HDLRunner to... commit | commitdiff | tree
2021-12-19 Luke Kenneth... break out when core is stopped in HDLRunner commit | commitdiff | tree
2021-12-18 Luke Kenneth... add link to XICS bugreport commit | commitdiff | tree
2021-12-18 Luke Kenneth... sort out reset signalling after tracking down Simulatio... commit | commitdiff | tree
2021-12-18 Luke Kenneth... add icache/dcache/mmu unit test for TestIssuer commit | commitdiff | tree
2021-12-18 Luke Kenneth... get instructions to re-run in issuer after I-Cache... commit | commitdiff | tree
2021-12-18 Luke Kenneth... forgot to connect up I-Cache to MMU commit | commitdiff | tree
2021-12-18 Luke Kenneth... move connection of bus.stall in icache.py, commit | commitdiff | tree
2021-12-18 Luke Kenneth... tidyup commit | commitdiff | tree
2021-12-18 Luke Kenneth... tlb_req_index is TLB_BITS long not TLB_SIZE commit | commitdiff | tree
2021-12-16 Luke Kenneth... whoops, a Simulation bug, dcache bus ack Signal needed... commit | commitdiff | tree
2021-12-16 Luke Kenneth... give names to MMU records commit | commitdiff | tree
2021-12-16 Luke Kenneth... set_mmu_spr was using the slow-SPR index for the regfile commit | commitdiff | tree
2021-12-16 Luke Kenneth... whoops remove duplicate code (cut/paste error) no harm... commit | commitdiff | tree
2021-12-15 Luke Kenneth... remove more unneeded code commit | commitdiff | tree
2021-12-15 Luke Kenneth... read MSR.PR and MSR.DR and update ICache priv/virt... commit | commitdiff | tree
2021-12-15 Luke Kenneth... remove more of SVP64 from TestIssuerInternalInOrder commit | commitdiff | tree
2021-12-15 Luke Kenneth... remove update of pc, msr and svstate from TestIssuerInOrder commit | commitdiff | tree
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