projects / soc.git / history
? search:
summary | shortlog | log | commit | commitdiff | tree
first ⋅ prev ⋅ next
Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / simple /
2023-09-12 Jacob Lifshayskip test_microwatt.BinaryTestCase.test_binary if file... tree | commitdiff
2023-07-27 Andrey MiroshnikovMakefile: Added rule for generating mw-compatible core... tree | commitdiff
2022-08-14 Luke Kenneth Casso... grr not a yield function tree | commitdiff
2022-08-14 Luke Kenneth Casso... add get_fpregs stub function to HDLstate tree | commitdiff
2022-07-06 Luke Kenneth Casso... update pinmux submodule, rename to "fabric" tree | commitdiff
2022-07-06 Luke Kenneth Casso... add fabric compatibility mode tree | commitdiff
2022-04-30 Luke Kenneth Casso... clear out DEC in core.cur_state.dec due to spurious... tree | commitdiff
2022-04-29 Luke Kenneth Casso... add option to set small cache sizes in tree | commitdiff
2022-04-16 Tobias Platenpart two of issuer_fix: read pspec.microwatt_old and... tree | commitdiff
2022-04-16 Tobias PlatenMerge ssh://git.libre-riscv.org:922/soc tree | commitdiff
2022-04-16 Tobias Platenpart one of issuer_fix: add parameter to issuer_verilog.py tree | commitdiff
2022-04-16 Luke Kenneth Casso... put the old microwatt compatibility back tree | commitdiff
2022-04-16 Luke Kenneth Casso... blegh. tree | commitdiff
2022-04-12 Tobias Platenissuer.py: add microwatt_old and microwatt_debug options tree | commitdiff
2022-04-09 Luke Kenneth Casso... add a new make target for setting coldboot firmware... tree | commitdiff
2022-04-03 Luke Kenneth Casso... correct default to zero string not zero int tree | commitdiff
2022-04-03 Luke Kenneth Casso... add alternative pc_reset argument to issuer_verilog.py tree | commitdiff
2022-03-12 Luke Kenneth Casso... introduce extra register of delay to split combinatoria... tree | commitdiff
2022-03-12 Luke Kenneth Casso... Revert "store cur_state.pc+4 in separate register to... tree | commitdiff
2022-03-12 Luke Kenneth Casso... store cur_state.pc+4 in separate register to help reduce tree | commitdiff
2022-03-06 Cesar StraussCopy the startup delay from issuer.py to inorder.py tree | commitdiff
2022-02-28 Luke Kenneth Casso... attempting to introduce an extra few clock cycles delay... tree | commitdiff
2022-02-27 Luke Kenneth Casso... add XLEN to issuer_verilog.py defaults to 64 tree | commitdiff
2022-02-20 Luke Kenneth Casso... put LDST go-store on a 1-clock delay to help with combi... tree | commitdiff
2022-01-21 Luke Kenneth Casso... sigh, monitor DEC/TB StateRegs "properly" so that the... tree | commitdiff
2022-01-21 Luke Kenneth Casso... whoops fix bug in setting of DEC/TB (State) in test_core.py tree | commitdiff
2022-01-20 Luke Kenneth Casso... whoops MFSPR DEC/TB was reading from FastRegs not StateRegs tree | commitdiff
2022-01-19 Luke Kenneth Casso... comments tree | commitdiff
2022-01-19 Luke Kenneth Casso... move DEC and TB into StateRegs, to make room in FastRegs tree | commitdiff
2022-01-18 Luke Kenneth Casso... add support for DMI debug read of FAST Regfile SPRs tree | commitdiff
2022-01-17 Luke Kenneth Casso... fix hrfid and mtmsrd so that it is identical to microwatt tree | commitdiff
2022-01-17 Luke Kenneth Casso... connect up DEC/TB FSM pauser from core to Issuer tree | commitdiff
2022-01-17 Luke Kenneth Casso... comments tree | commitdiff
2022-01-17 Luke Kenneth Casso... whitespace tree | commitdiff
2022-01-17 Luke Kenneth Casso... add pause_dec_tb signal (not very sophisticated) to... tree | commitdiff
2022-01-17 Luke Kenneth Casso... add signal for pausing the DEC/TB FSM to IssuerBase tree | commitdiff
2022-01-15 Luke Kenneth Casso... enable both linux-5.7 tests tree | commitdiff
2022-01-14 Luke Kenneth Casso... second test for linux-5.7 tree | commitdiff
2022-01-12 Luke Kenneth Casso... add allow-overlap option to issuer_verilog.py tree | commitdiff
2022-01-09 Luke Kenneth Casso... grab the LDST request address for microwatt verilator... tree | commitdiff
2022-01-09 Luke Kenneth Casso... add linux-5.7 unit test which showed a silly error: tree | commitdiff
2022-01-07 Luke Kenneth Casso... add msr_o to issuer in microwatt_compat mode tree | commitdiff
2022-01-05 Luke Kenneth Casso... add easy-to-access debug reporting of instruction and PC tree | commitdiff
2022-01-04 Luke Kenneth Casso... fix DriverConflict over MSR write in Issuer/Core by... tree | commitdiff
2022-01-04 Luke Kenneth Casso... remove FetchFSM from TestIssuer (it served its purpose... tree | commitdiff
2022-01-03 Luke Kenneth Casso... doh, bus-hack was the wrong way round. *output* the... tree | commitdiff
2022-01-03 Luke Kenneth Casso... sigh, microwatts wishbone bus usage is non-wishbone... tree | commitdiff
2022-01-03 Luke Kenneth Casso... sigh have to allow external clocks and reset mess even... tree | commitdiff
2022-01-03 Luke Kenneth Casso... give module appropriate top-level name in microwatt... tree | commitdiff
2022-01-03 Luke Kenneth Casso... add missing ext_irq signal to testissuer in microwatt... tree | commitdiff
2022-01-03 Luke Kenneth Casso... adding an extra option to issuer_verilog.py to be able... tree | commitdiff
2022-01-03 Luke Kenneth Casso... bring external irq out for microwatt-compatible mode... tree | commitdiff
2022-01-03 Cesar StraussOn inorder.py, after Execute, update the PC and go... tree | commitdiff
2021-12-30 Luke Kenneth Casso... rename nia to cia in MMU input record and mmu FSM tree | commitdiff
2021-12-28 Cesar StraussAdd an --inorder option to test_issuer.py tree | commitdiff
2021-12-27 Cesar StraussFix indentation tree | commitdiff
2021-12-25 Luke Kenneth Casso... add mmu.bin test2 to much simpler test_loadstore1.py tree | commitdiff
2021-12-25 Luke Kenneth Casso... move microwatt mmu.bin test 3 page table to test pageta... tree | commitdiff
2021-12-25 Luke Kenneth Casso... wait for MMU "done" when setting PRTBL and PIDR tree | commitdiff
2021-12-25 Luke Kenneth Casso... add microwatt mmu.bin regression test test_mmu_3 tree | commitdiff
2021-12-24 Luke Kenneth Casso... enable instruction redirect in mmu ifetch test tree | commitdiff
2021-12-23 Luke Kenneth Casso... allow MSR reset to default to a value set by issuer_ver... tree | commitdiff
2021-12-23 Luke Kenneth Casso... pass in msr_reset to issuer_verilog.py tree | commitdiff
2021-12-23 Cesar StraussRemove extra wait on core_stop_o at end of Execute. tree | commitdiff
2021-12-23 Cesar StraussRe-enable core stopped signal when stopped. tree | commitdiff
2021-12-22 Luke Kenneth Casso... fix issues with running core in DMI "stopped" status... tree | commitdiff
2021-12-22 Luke Kenneth Casso... whoops, use MSR.IR for I-Cache fetch! tree | commitdiff
2021-12-21 Luke Kenneth Casso... continue to assert PC in FetchFSM if needed tree | commitdiff
2021-12-21 Luke Kenneth Casso... enable I-Cache wishbone memory type in issuer_verilog... tree | commitdiff
2021-12-21 Luke Kenneth Casso... whoops issuer_verilog.py enabling mmu has to pass micro... tree | commitdiff
2021-12-21 Luke Kenneth Casso... for each unit test case in test_issuer_mmu_data_path... tree | commitdiff
2021-12-21 Luke Kenneth Casso... test_issuer_mmu_data_path.py needs to use wb_get because of tree | commitdiff
2021-12-20 Luke Kenneth Casso... set up DAR correctly in unit tests, added set_ldst_spr... tree | commitdiff
2021-12-19 Luke Kenneth Casso... add hard stop address in ifetch unit test, bit of a... tree | commitdiff
2021-12-19 Luke Kenneth Casso... set terminate if core terminate requested tree | commitdiff
2021-12-19 Luke Kenneth Casso... add DMI STOPADDR register and use it in HDLRunner to... tree | commitdiff
2021-12-19 Luke Kenneth Casso... break out when core is stopped in HDLRunner tree | commitdiff
2021-12-18 Luke Kenneth Casso... sort out reset signalling after tracking down Simulatio... tree | commitdiff
2021-12-18 Luke Kenneth Casso... add icache/dcache/mmu unit test for TestIssuer tree | commitdiff
2021-12-18 Luke Kenneth Casso... get instructions to re-run in issuer after I-Cache... tree | commitdiff
2021-12-16 Luke Kenneth Casso... set_mmu_spr was using the slow-SPR index for the regfile tree | commitdiff
2021-12-16 Luke Kenneth Casso... whoops remove duplicate code (cut/paste error) no harm... tree | commitdiff
2021-12-15 Luke Kenneth Casso... remove more unneeded code tree | commitdiff
2021-12-15 Luke Kenneth Casso... read MSR.PR and MSR.DR and update ICache priv/virt... tree | commitdiff
2021-12-15 Luke Kenneth Casso... remove more of SVP64 from TestIssuerInternalInOrder tree | commitdiff
2021-12-15 Luke Kenneth Casso... remove update of pc, msr and svstate from TestIssuerInOrder tree | commitdiff
2021-12-15 Luke Kenneth Casso... move update of pc, msr and svstate into TestIssuerBase tree | commitdiff
2021-12-15 Luke Kenneth Casso... comment-out TestIssuerInternalInorder for now tree | commitdiff
2021-12-15 Luke Kenneth Casso... move alternative TestIssuerInternalInOrder to new file tree | commitdiff
2021-12-15 Luke Kenneth Casso... split out common elaboratable code from TestIssuer, tree | commitdiff
2021-12-15 Luke Kenneth Casso... big split-out of common functions in TestIssuer to... tree | commitdiff
2021-12-15 Luke Kenneth Casso... simplifying / tidyup of TestIssuer to get CoreState tree | commitdiff
2021-12-15 Luke Kenneth Casso... sort out MSR, read/write in same way as PC/SVSTATE... tree | commitdiff
2021-12-15 Luke Kenneth Casso... whoops accidentally commented out setup of instructions tree | commitdiff
2021-12-15 Luke Kenneth Casso... get fetch_failed working with no MMU tree | commitdiff
2021-12-14 Luke Kenneth Casso... trying to get TestIssuer FSM to respond correctly to... tree | commitdiff
2021-12-14 Luke Kenneth Casso... update wb_get memory with instructions if required tree | commitdiff
2021-12-13 Luke Kenneth Casso... request a flush of icache to clear the instruction... tree | commitdiff
2021-12-12 Luke Kenneth Casso... set and reset instruction fault so it does not occur... tree | commitdiff
2021-12-12 Luke Kenneth Casso... when an exception happens, if it is a fetch_failed... tree | commitdiff
next