2021-02-23 |
Luke Kenneth Casso... | add note that SVSTATE has changed, this will allow... |
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2021-02-22 |
Luke Kenneth Casso... | move setting of NIA into fetch FSM in TestIssuer |
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2021-02-22 |
Luke Kenneth Casso... | moving PC-setting (NIA) out of execute_fsm in TestIssuer |
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2021-02-22 |
Luke Kenneth Casso... | rename inter-FSM handshake signals in TestIssuer |
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2021-02-21 |
Luke Kenneth Casso... | err trying to put in some FSM handshake signals, gettin... |
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2021-02-21 |
Luke Kenneth Casso... | comment for where SVSTATE FSM should go |
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2021-02-21 |
Luke Kenneth Casso... | move execute_fsm to separate function in TestIssuer |
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2021-02-21 |
Luke Kenneth Casso... | move fetch_fsm to separate function in TestIssuer |
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2021-02-21 |
Luke Kenneth Casso... | add JTAG enable/disable of 4k SRAMs |
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2021-02-20 |
Luke Kenneth Casso... | add QTY 4of 4k SRAMs SPBlock512W64B8W to TestIssuer... |
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2021-02-20 |
Luke Kenneth Casso... | whoops spelling error |
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2021-02-20 |
Luke Kenneth Casso... | add (unused) code for writing out SVSTATE in TestIssuer |
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2021-02-15 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-02-14 |
Cesar Strauss | Remove obsolete comment |
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2021-02-14 |
Luke Kenneth Casso... | add comments to TestIssuer |
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2021-02-14 |
Luke Kenneth Casso... | add SVSTATE reading to TestIssuer |
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2021-02-14 |
Luke Kenneth Casso... | add extra FSM explanatory comments to TestIssuer |
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2021-02-13 |
Luke Kenneth Casso... | use function for getting instruction from 32/64 bit... |
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2021-02-13 |
Cesar Strauss | Fetch and decode the SVP64 prefix |
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2021-02-11 |
Luke Kenneth Casso... | comments in TestIssuer for SVP64PrefixDecoder |
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2021-02-06 |
Cesar Strauss | Extract the fetch FSM out from the main FSM |
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2020-11-13 |
Luke Kenneth Casso... | reduce clkcsel ls180 width (2 pins), rename pll_18... |
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2020-11-13 |
Luke Kenneth Casso... | rename and add pll lock signal to ls180 |
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2020-11-10 |
Luke Kenneth Casso... | remove ClockSelect module, use DummyPLL |
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2020-10-22 |
Luke Kenneth Casso... | add query about cross-domain on the JTAG enable of WB |
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2020-10-22 |
Luke Kenneth Casso... | add JTAG enable/disable of wishbone to TestIssuer |
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2020-10-15 |
Luke Kenneth Casso... | wrong pspec variable in selecting pll clock |
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2020-10-15 |
Luke Kenneth Casso... | sorting out missing clock somewhere |
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2020-10-11 |
Luke Kenneth Casso... | add way to bypass PLL for ECP5 and sim |
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2020-10-11 |
Luke Kenneth Casso... | comment out XICS/GPIO interrupt test, causes ECP5 litex... |
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2020-10-11 |
Luke Kenneth Casso... | litex sim.py operational |
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2020-10-07 |
Luke Kenneth Casso... | reorder / reorganise reset signals slightly |
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2020-10-06 |
Luke Kenneth Casso... | add sdr bypass routing via JTAG boundary scan |
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2020-10-04 |
Luke Kenneth Casso... | significant reorg of the litex pinspecs to use pinmux... |
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2020-10-03 |
Luke Kenneth Casso... | minor reorg on JTAG, allow alternative pinset dict... |
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2020-10-01 |
Luke Kenneth Casso... | add clksel, pll to ls180 |
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2020-10-01 |
Luke Kenneth Casso... | create dummy PLL block, connect up to core and clock... |
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2020-09-26 |
Luke Kenneth Casso... | DMI-to-JTAG needed to be "sync" to get ack/resp right |
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2020-09-22 |
Luke Kenneth Casso... | move dmi_sim to separate module |
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2020-09-22 |
Luke Kenneth Casso... | add jtag interface to issuer_verilog |
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2020-09-08 |
Luke Kenneth Casso... | create a special subset of Decoder Record for storing... |
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2020-09-08 |
Luke Kenneth Casso... | pass in state into PowerDecode2, save on eqs and wires |
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2020-09-07 |
Luke Kenneth Casso... | add per-FU PowerDecoders. should now be subsettable |
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2020-09-06 |
Luke Kenneth Casso... | copy dec SPR into decoder cur_state |
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2020-09-06 |
Luke Kenneth Casso... | wark-wark, fast regs is binary-addressed |
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2020-09-06 |
Luke Kenneth Casso... | add comments for DEC / TB |
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2020-09-06 |
Luke Kenneth Casso... | add a DEC/TB FSM to TestIssuer |
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2020-09-05 |
Luke Kenneth Casso... | add comments on MSR read |
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2020-09-05 |
Luke Kenneth Casso... | move GPIO IRQ to 15 to match microwatt modifications |
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2020-09-05 |
Luke Kenneth Casso... | MSR read in INSN_READ only occurs for 1 cycle |
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2020-09-05 |
Luke Kenneth Casso... | sync on ICP eint |
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2020-09-05 |
Luke Kenneth Casso... | connect XICS core irq to Decode2 eint |
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2020-09-05 |
Luke Kenneth Casso... | add simple GPIO peripheral to verilog TestIssuer |
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2020-09-04 |
Luke Kenneth Casso... | bring out XICS ICS interrupt levels so that they can... |
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2020-09-04 |
Luke Kenneth Casso... | adding option to include XICS external interrupts. |
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2020-08-29 |
Luke Kenneth Casso... | add XER read via DMI interface to sim.py |
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2020-08-29 |
Luke Kenneth Casso... | add hack to get at XER through DMI interface |
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2020-08-25 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
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2020-08-25 |
Luke Kenneth Casso... | add CR read to DMI interface |
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2020-08-24 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
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2020-08-23 |
Luke Kenneth Casso... | bring "core stopped" signal out through DMI interface |
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2020-08-21 |
Luke Kenneth Casso... | get litex sim enabled with 32-bit wishbone bus |
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2020-08-16 |
Luke Kenneth Casso... | read delay on getting regfile data |
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2020-08-15 |
Luke Kenneth Casso... | rather big change to interaction between regfile and... |
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2020-08-14 |
Luke Kenneth Casso... | ha! "state" (pc, msr) not properly passed to core |
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2020-08-14 |
Luke Kenneth Casso... | drop in insn_state synchronously in issuer, at same... |
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2020-08-14 |
Luke Kenneth Casso... | finally, fix decoder combinatorial loop |
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2020-08-14 |
Luke Kenneth Casso... | sync up the core decode-execute state, |
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2020-08-14 |
Luke Kenneth Casso... | move instruction decoder out of core |
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2020-08-14 |
Luke Kenneth Casso... | sort out instruction stop/cancel when adding a new... |
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2020-08-13 |
Luke Kenneth Casso... | fix dmi reg read |
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2020-08-13 |
Luke Kenneth Casso... | sync on pc writing when changed |
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2020-08-13 |
Luke Kenneth Casso... | sigh. convert INT regfile to binary addressing |
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2020-08-11 |
Luke Kenneth Casso... | reduce regfile ports by creating separate STATE regfile |
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2020-08-11 |
Luke Kenneth Casso... | reducing regfile port usage by sharing read ports |
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2020-08-10 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
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2020-08-09 |
Luke Kenneth Casso... | fix combinatorial loop in ldst compunit |
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2020-08-09 |
Luke Kenneth Casso... | use rising edge detection on st go_i/rel_o |
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2020-08-09 |
Luke Kenneth Casso... | get rid of MSR read combinatorial loop |
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2020-08-09 |
Luke Kenneth Casso... | delay go_st by one cycle, break combinatorial loop |
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2020-08-05 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
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2020-08-05 |
Luke Kenneth Casso... | add div FSM as default for test_issuer in verilog and... |
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2020-08-04 |
Luke Kenneth Casso... | read/set pc outside of FSM so that DMI interface can... |
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2020-08-04 |
Luke Kenneth Casso... | whoops must output NIA not PC to debug DMI query in... |
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2020-08-04 |
Luke Kenneth Casso... | add DMI debug interface to libresoc litex sim |
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2020-08-03 |
Luke Kenneth Casso... | add quick demo/test of reading DMI reg 9 |
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2020-08-03 |
Luke Kenneth Casso... | pass state (MSR/PC) around between PowerDecode2, DMI... |
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2020-08-03 |
Luke Kenneth Casso... | use new soc.config.state CoreState class in DMI and... |
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2020-08-03 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-08-03 |
Luke Kenneth Casso... | change over to DMI debug start/stop interface |
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2020-07-31 |
Luke Kenneth Casso... | restrict external port list further in test_issuer |
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2020-07-30 |
Luke Kenneth Casso... | core_start/stop/endian were inverted (output) |
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2020-07-30 |
Luke Kenneth Casso... | ha! have to explicitly specify the ports when writing... |
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2020-07-29 |
Luke Kenneth Casso... | bit of a big change: add prefixes "cu_" to all CompUnit... |
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2020-07-23 |
Luke Kenneth Casso... | allow imem to be 64/32 bit wide |
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2020-07-22 |
Luke Kenneth Casso... | missing ports from issuer, when doing verilog |
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2020-07-22 |
Luke Kenneth Casso... | reduce number of FastRegs read ports |
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2020-07-21 |
Luke Kenneth Casso... | add PC (CIA) to PowerDecode2 "state" for passing into... |
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2020-07-19 |
Luke Kenneth Casso... | expose core_stop_i to outside as well |
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2020-07-19 |
Luke Kenneth Casso... | set go_insn_i to non-resetless |
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