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clear out DEC in core.cur_state.dec due to spurious interrupt.
[soc.git]
/
src
/
soc
/
simple
/
issuer_verilog.py
2022-04-29
Luke Kenneth Casso...
add option to set small cache sizes in
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2022-04-16
Tobias Platen
Merge ssh://git.libre-riscv.org:922/soc
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2022-04-16
Tobias Platen
part one of issuer_fix: add parameter to issuer_verilog.py
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2022-04-03
Luke Kenneth Casso...
correct default to zero string not zero int
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2022-04-03
Luke Kenneth Casso...
add alternative pc_reset argument to issuer_verilog.py
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2022-02-27
Luke Kenneth Casso...
add XLEN to issuer_verilog.py defaults to 64
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2022-01-12
Luke Kenneth Casso...
add allow-overlap option to issuer_verilog.py
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2022-01-09
Luke Kenneth Casso...
add linux-5.7 unit test which showed a silly error:
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2022-01-03
Luke Kenneth Casso...
sigh have to allow external clocks and reset mess even...
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2022-01-03
Luke Kenneth Casso...
give module appropriate top-level name in microwatt...
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2022-01-03
Luke Kenneth Casso...
adding an extra option to issuer_verilog.py to be able...
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2021-12-23
Luke Kenneth Casso...
pass in msr_reset to issuer_verilog.py
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2021-12-21
Luke Kenneth Casso...
enable I-Cache wishbone memory type in issuer_verilog...
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2021-12-21
Luke Kenneth Casso...
whoops issuer_verilog.py enabling mmu has to pass micro...
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2021-05-01
Luke Kenneth Casso...
enable issuer_verilog.py to generate new MMU/DCache...
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2021-04-20
Luke Kenneth Casso...
add enable MMU option to issuer_verilog.py
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2021-03-30
Alain D D Williams
Merge branch 'master' of git.libre-soc.org:soc
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2021-03-28
Luke Kenneth Casso...
add option to reduce number of regfile ports (get DFFs...
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2021-03-08
Luke Kenneth Casso...
add option in TestRunner to disable svp64 via commandli...
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2021-02-20
Luke Kenneth Casso...
add option for QTY 4x 4k SRAM blocks (not added yet...
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2020-11-13
Luke Kenneth Casso...
add enable/disable arguments (not ideal but it works...
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2020-10-21
Cole Poirier
versa_ecp5 adds ability to build and load for ulx3s85f...
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2020-10-15
Luke Kenneth Casso...
sorting out missing clock somewhere
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2020-10-15
Luke Kenneth Casso...
use "enable" and set default actions in getopt
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2020-10-14
Cole Poirier
issuer_verilog.py update to use commandline args using...
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2020-10-11
Luke Kenneth Casso...
add way to bypass PLL for ECP5 and sim
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2020-10-11
Luke Kenneth Casso...
litex sim.py operational
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2020-09-28
Luke Kenneth Casso...
add "nocore" option to build verilog
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2020-09-28
Luke Kenneth Casso...
switch off internal gpio (testing)
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2020-09-22
Luke Kenneth Casso...
add jtagremote to litex sim, add new "variant" to core...
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2020-09-22
Luke Kenneth Casso...
add jtag interface to issuer_verilog
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2020-09-19
Luke Kenneth Casso...
remove the gpio peripheral which was previously hard...
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2020-09-05
Luke Kenneth Casso...
add simple GPIO wishbone bus to litex sim.py
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2020-09-05
Luke Kenneth Casso...
add simple GPIO peripheral to verilog TestIssuer
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2020-09-04
Luke Kenneth Casso...
adding option to include XICS external interrupts.
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2020-08-24
Cole Poirier
Merge branch 'master' of git.libre-soc.org:soc
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2020-08-21
Luke Kenneth Casso...
testing 64-bit wishbone bus after 32-bit *still* fails...
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2020-08-21
Luke Kenneth Casso...
get litex sim enabled with 32-bit wishbone bus
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2020-08-14
Luke Kenneth Casso...
put multi-ports back (for read) on int and fast regfiles
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2020-08-05
Cole Poirier
Merge branch 'master' of git.libre-soc.org:soc
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2020-08-05
Luke Kenneth Casso...
add div FSM as default for test_issuer in verilog and...
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2020-07-30
Luke Kenneth Casso...
ha! have to explicitly specify the ports when writing...
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2020-07-23
Luke Kenneth Casso...
support 32-bit mem width setting
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2020-07-19
Luke Kenneth Casso...
add issuer verilog generator
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